NCP1215
http://onsemi.com
7
APPLICATION INFORMATION
The NCP1215 implements a current mode SMPS with a
variable OFF−time dependant upon output power demand.
It can be seen from the typical application that NCP1215 is
designed to operate with a minimum number of external
component. The NCP1215 incorporates the following
features:
•
Frequency Foldback: Since the switch−off time
increases when power demand decreases, the switching
frequency naturally diminishes in light load conditions.
This helps to minimize switching losses and offers
excellent standby power performance.
•
Very Low Startup Current: The patented internal
supply block is specially designed to offer a very low
current consumption during startup. It allows the use of
a very high value external startup resistor, greatly
reducing dissipation, improving efficiency and
minimizing standby power consumption.
•
Natural Frequency Dithering: The quasi−fixed T
on
mode of operation improves the EMI signature since
the switching frequency varies with the natural bulk
ripple voltage.
•
Peak Current Compression: As the load becomes
lighter, the frequency decreases and can enter the
audible range. To avoid exciting transformer
mechanical resonances, hence generating acoustic
noise, the NCP1215 includes a patented technique,
which reduces the peak current as power goes down.
As such, inexpensive transformer can be used without
having noise problems.
•
Negative Primary Current Sensing: By sensing
the total current, this technique does not modify the
MOSFET driving voltage (Vgs) while switching.
Furthermore, the programming resistor together with the
pin capacitance, forms a residual noise filter which
blanks spurious spikes. Also fixing primary current level
to a maximum value sets the maximum power limit.
•
Programmable Primary Current Sense: It offers a
second peak current adjustment variable which improves
the design flexibility.
•
Secondary or Primary Regulation: The feedback
loop arrangement allows simple secondary or primary
side regulation without significant additional external
components.
A detailed description of each internal block within the IC
is given in the following.
Feedback Loop Control
The main task of the Feedback Loop Block is to control
the SMPS output voltage through the change of primary
switch OFF time interval. It sets the peak voltage of the
timing capacitor, which varies upon the output power
demand. Figure 13 shows the simplified internal schematic:
Figure 13. Feedback Loop − OFF Time Control
FB
17 k
Current
Mirror
1:1
Current
Mirror
1:1
−
+
To OFF
Time
Comparator
45 k
V
offset
V
CC
The voltage feedback signal is sensed as a current injected
through the FB pin.
Figure 14. FB Loop Transfer Characteristic
OFF−T
ime
Comparator Input V
oltage
V
DD
V
offset
0
m
A
FB Pin Sink Current
The transfer characteristic (output voltage to input
current) of the feedback loop control block can be seen in
Figure 14. V
DD
refers to the internal stabilized supply
whereas the offset value sets the maximum switching
frequency in lack of optocoupler current (e.g. an output
short−circuit).
To keep the switching frequency above the audio range in
light load condition the FB pin also regulates in certain range
the peak primary current. The corresponding block diagram
can be seen from Figure 15.
