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NB3N1200KMNGEVB, NB3W1200LMNGEVB

http://onsemi.com

7

Graphical User Interface (GUI)

USB & I

2

C/SMBus Interface

The NB3N1200K EVB has an on-board I

2

C/SMBus

interface circuitry located in the upper left section of the
board.

This circuitry will interface with the software program

and the device via the SDA and SCL input pins, and can
control all twelve of the OE_n# pins, PLL Mode and
Frequency Select directly from the GUI.

SCL & SDA

The SMBus Clock (SCL) and Data (SDA) pins are

exercised through the on-board I

2

C interface.

In order to enable the I

2

C control of the DUT, header

jumpers J63 & J64 must be shorted.

The I

2

C/SMBus interface circuitry is powered separately

from the USB type-B connection and is isolated from device
VDD and VDDIO.

The SDA and SCL pins can also be externally accessed by

an off-board programmer, allowing other SMBus emulators
to be used to program the DUT. If used, remove both jumpers
J63 & J64. “Test-point anvils” TP5 & TP6 are available for
external control of the device with the use with mini-grabber
cables.

BOARD FEATURES

Single Board Design/Layout for NB3N1200K or
NB3W1200L:

•

The single board design and layout accommodates the
electrical characterization of either the NB3N1200K
(standard HCSL outputs) or the NB3W1200L (HCSL
Push-Pull outputs).

•

Incorporates on-board I

2

C/SMBus interface circuitry

powered from a USB connection, minimizing cabling.

•

Convenient and compact board layout.

•

3.3 V power supply device operation.

•

Differential inputs/outputs signals are accessed via
SMA connectors or high impedance probes.

Other Board Features

There are no vias on the high-speed differential I/O metal

traces so as to eliminate via impedance and stub affects.

Board stand-offs are installed.

Board Layout

The NB3N1200K QFN-64 Evaluation Board provides

a high bandwidth, 50-

W

 controlled trace impedance

environment (100-

W

 line-to-line differential) and is

implemented in four layers.

•

All layers are constructed with FR4 dielectric material.

•

The first layer is the primary signal layer, including all
of the differential inputs and outputs.

•

The second layer is the ground plane. It is dedicated for
the DUT ground/SMA ground plane.

•

The third layer is dedicated as the power plane.
A portion of this 3

rd

 layer is designated for the device

VDD and VDDIO power planes.

•

The fourth layer contains control lines, power supply
banana jacks and device power pin bypass capacitors.

Layer Stack

•

L1 (Top) Signal

•

L2 Device Ground and SMA Ground

•

L3 VDD, VDDIO (Separate Device Power Supplies)

•

L4 (Bottom), Power Supply By-pass Capacitors,
Control Pin Traces and Banana Jacks

Figure 11. NB3N1200KMNGEVB and NB3W1200LMNGEVB Evaluation Board Layer Stack-Up

Содержание NB3N1200K

Страница 1: ... differential outputs are loaded terminated and can be monitored with a high impedance probe as explained later in the manual The NB3N1200K Evaluation Board schematic is the same as the NB3W1200L schematic except the 1200L has some components depopulated DNI per the 1200L BOM The NB3W1200LMNGEVB does not have RP resistors installed on its differential Push Pull outputs The NB3W1200LMNGEVB does not...

Страница 2: ...ice Pin Power Supply Connector Power Supply VDD 3 3 V VDDIO 1 05 V to 3 3 V GND 0 V Figure 2 Power Supply Connections Dual Power Supplies 3 3 V 0 V VDD GND 3 3 V 1 05 V to 3 3 V 1 05 V to 3 3 V VDDIO Single Power Supply 3 3 V 0 V VDD VDDIO GND 3 3 V Figure 3 Typical Lab Test Set Up 3 3 V 3 3 V 0 V INb IN Oscilloscope Signal Generator OUTb OUT Power Up Sequence 1 Turn on power supply 3 3 V VDD VDDI...

Страница 3: ...ged manually with a H L jumper header H VDD L GND Tri Level Input Pins HBW_BYPASS_LBW SA0 and SA1 The three tri level input pins HBW_BYPASS_LBW SA0 and SA1 have selectable with jumper 4 7 k ohm pull up to VDD and 4 7 k ohm pull down to GND resistors No jumper defaults to open float For a HIGH Level Put Jumper to High For a LOW Level Put Jumper to Low For a MID Level Put Jumper to both High and Low...

Страница 4: ...shed via the USB when the OE_n jumper is installed on the middle header position See Figure 6 Figure 6 OE_n Pins Schematic PCB Configuration OE OE VDD J47 37 1 2 3 4 5 6 USB GUI HI Jumper to VDD USB Jumper to Mid LO Jumper to GND 100M_133M Frequency Selection J55 The 100M_133M frequency selection pin can be controlled manually with the High Low header jumper J55 H 100 MHz L 133 MHz Figure 7 100M_1...

Страница 5: ... 2 pF capacitors are installed on all outputs Rs Rp pads are located close to the DUT Rs 33 W is installed for both the NB3N1200K and NB3W1200L NB3N1200K HCSL Outputs RP is not installed on the six output pair with long metal traces to SMA connectors Use 50 W to GND of the oscilloscope head for RP Rp is installed 50 W to GND on the short metal traces without SMA connectors and will use Hi Z probes...

Страница 6: ...using Hi Z probes As a feature an optional component can be installed on each output ie additional capacitance loading etc The following figures describe the boards output features Figure 10 Differential Outputs Schematic PCB Configuration Use Hi Z Probe Scope for NB3W1200L From DUT Output Ground Hi Z probe Optional component to Ground if needed when shorted to output trace CLoad 2 pF installed Se...

Страница 7: ...puts or the NB3W1200L HCSL Push Pull outputs Incorporates on board I2C SMBus interface circuitry powered from a USB connection minimizing cabling Convenient and compact board layout 3 3 V power supply device operation Differential inputs outputs signals are accessed via SMA connectors or high impedance probes Other Board Features There are no vias on the high speed differential I O metal traces so...

Страница 8: ...33M_N 4 HBW_BYP_LBW 5 PWRGD 6 SA0 11 SA1 14 PR7 R7 49 9 1 2 R27 49 9 1 2 R124 0 1 2 C27 10uF 10V 1 2 R79 4 7K 1 2 R47 49 9 1 2 C13 2 0pF 1 2 J21 DIF10 TP19 R85 4 7K 1 2 J48 1 2 3 4 5 6 J56 1 2 3 C18 2 0pF 1 2 J11 DIF5 R71 49 9 1 2 J4 DIF1 C34 100nF 1 2 C26 2 0pF 1 2 97 49 9 1 2 R127 0 1 2 TP26 R99 33 1 2 R73 33 1 2 R125 0 1 2 J70 SA1 LO 1 2 R49 33 1 2 TP15 C14 2 0pF 1 2 R11 49 9 1 2 TP20 R9 33 1 2...

Страница 9: ... 10 VREGIN 50 VREGOUT 49 VCORE 12 VCORE 37 VCORE 64 DM 7 DP 8 GND 1 GND 5 GND 11 GND 15 GND 25 GND 35 GND 47 GND 51 TEST 13 EECS 63 EECLK 62 EEDATA 61 REF 6 RESET_N 14 SUSPEND_N 36 PWREN_N 60 OSCI 2 OSCO 3 GPIOH7 34 GPIOH6 33 GPIOH5 32 GPIOH4 30 GPIOH3 29 GPIOH2 28 GPIOH1 27 GPIOH0 26 J63 1 2 U4 NCP4586 3 3V IN 1 OUT 5 GND 2 EN 3 NC 4 J64 1 2 C59 1uF 10V 1 2 C45 100nF 1 2 C39 100nF 1 2 C50 10nF 16...

Страница 10: ...601SN1D Yes Yes J3 J6 J11 J14 J19 J22 J37 J38 14 RF Connectors PC END MT JCK GLD 062 SMA_END_LA UNCH_0 062 Johnson Components 142 0701 801 Yes Yes J43 J44 J47 J48 J51 J52 6 Header Header Thru Hole 2 3 FCI 67996 206HLF Yes Yes J56 J55 2 Header Header 3 pin 3 pin Header thru hole 0 1 3M 961103 6404 AR Yes Yes J59 1 Banana Jack Thru Hole Red CON2_571 050 0_DELTRON Deltron 571 0500 Yes Yes J60 1 Banan...

Страница 11: ...onic ERJ 3GEYJ2R2V Yes Yes R107 1 Resistor 475 W 1 0402 Panasonic ERJ 2RKF4750X Yes Yes R108 R109 2 Resistor 82 5 W 1 0402 Panasonic ERJ 2RKF82R5X Yes Yes R110 R111 R114 R116 R118 6 Resistor 10 kW 5 0402 Panasonic ERJ 2GEJ103X Yes Yes R112 R113 R121 R132 14 Resistor 0 W Jumper 0201 Panasonic ERJ 1GE0R00C Yes Yes R115 1 Resistor 12 kW 1 0402 Panasonic ERJ 2RKF1202X Yes Yes R119 1 Resistor 470 W 5 0...

Страница 12: ...AG601SN1D Yes Yes J3 J6 J11 J14 J19 J22 J37 J38 14 RF Connectors PC END MT JCK GLD 062 SMA_END_LA UNCH_0 062 Johnson Components 142 0701 801 Yes Yes J43 J44 J47 J48 J51 J52 6 Header Header Thru Hole 2 3 FCI 67996 206HLF Yes Yes J56 J55 2 Header Header 3 pin 3 pin Header thru hole 0 1 3M 961103 6404 AR Yes Yes J59 1 Banana Jack Thru Hole Red CON2_571 050 0_DELTRON Deltron 571 0500 Yes Yes J60 1 Ban...

Страница 13: ...es SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating ...

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