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©

 Semiconductor Components Industries, LLC, 2012

January, 2012 

 Rev. 2

1

Publication Order Number:

EVBUM2056/D

ECLSOIC8EVB

Evaluation Board User's
Manual for High Frequency
SOIC 8

INTRODUCTION

ON Semiconductor has developed an evaluation board for

the devices in 8

lead SOIC package. These evaluation

boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 8

lead SOIC device

samples. The board provides a high bandwidth 50 

W

controlled impedance environment. The pictures in Figure 1
show the top and bottom view of the evaluation board, which
can be configured in several different ways, depending on
device under test (See Table 1. Configuration List).

This evaluation board manual contains:

Information on 8

lead SOIC Evaluation Board

Assembly Instructions

Appropriate Lab Setup

Bill of Materials

This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.

Board Lay

Up

The 8

lead SOIC evaluation board is implemented in four

layers  with  split  (dual) power supplies (Figure 2.
Evaluation Board Lay

up). For standard ECL lab setup and

test, a split (dual) power supply is essential to enable the
50 

W

 internal impedance in the oscilloscope as a termination

for ECL devices. The first layer or primary trace layer is
0.008

 thick Rogers RO4003 material, which is designed to

have equal electrical length on all signal traces from the
device under the test (DUT) to the sense output. The second
layer is the 1.0 oz copper ground plane and a portion of the
plane is the V

EE

 power plane. The FR4 dielectric material is

placed between second and third layer and between third and
fourth layer. The third layer is also 1.0 oz copper ground
plane and a portion of this layer is V

CC

 power plane. The

fourth layer is the secondary trace layer.

Figure 1. Top and Bottom View of the 8

lead SOIC Evaluation Board

http://onsemi.com

EVAL BOARD USER’S MANUAL

Содержание ECLSOIC8EVB

Страница 1: ...e used in conjunction with the device data sheet which contains full technical details on the device specifications and operation Board Lay Up The 8 lead SOIC evaluation board is implemented in four l...

Страница 2: ...rent configurations The input output and power pin layout of the evaluation board is shown in Figure 3 The evaluation board has at least eleven possible configurable options Table 1 list the devices a...

Страница 3: ...32D See Figure 7 4 MC100LVEL33D See Figure 7 4 MC100LVEL51D See Figure 4 1 MC100LVEL58D See Figure 8 5 MC100LVELT22D See Figure 11 8 MC100LVELT23D See Figure 12 9 ECLinPS PlusE Device Comments Configu...

Страница 4: ...VEE and GND The VCC clip connects directly to pin 8 of the device The VEE clip connects directly to pin 5 of the device There are two GND clip footprints which can be connected to the ground plane of...

Страница 5: ...Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4 MC10EL01D MC100EL01D Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes Yes MC10EL05D MC100EL05D MC10EL31D MC100EL31D MC10EL35D...

Страница 6: ...Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4 MC10EL04D MC100EL04D No No Yes Yes Yes Yes No No Yes Yes Yes No Yes No Yes Yes MC10EL07D MC100EL0...

Страница 7: ...ure 6 Configuration 3 Schematic R6 50 W Table 6 Configuration 3 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Device J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4 MC10EL11D MC100EL11D Yes No Yes N...

Страница 8: ...in 8 Optional Figure 7 Configuration 4 Schematic R2 50 W R1 50 W Table 7 Configuration 4 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4 MC10EL32...

Страница 9: ...gure 8 Configuration 5 Schematic R3 50 W R2 50 W Table 8 Configuration 5 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4 MC100EP16VCD No No Yes Y...

Страница 10: ...3 Pin 2 Pin 1 Pin 5 Pin 6 Pin 7 Pin 8 Figure 9 Configuration 6 Translator Schematic Table 9 Configuration 6 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J...

Страница 11: ...Figure 10 Configuration 7 Translator Schematic Unloaded Testing Condition R2 50 W Table 10 Configuration 7 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J...

Страница 12: ...in 6 Pin 7 Pin 8 Figure 11 Configuration 8 Translator Schematic J6 J4 J1 R7 50 W optional Table 11 Configuration 8 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3...

Страница 13: ...iguration 9 Translator Schematic Unloaded Testing Condition R1 50 W R2 50 W R3 50 W R4 50 W Table 12 Configuration 9 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C...

Страница 14: ...Figure 13 Configuration 10 Translator Schematic Unloaded Testing Condition R3 50 W Table 13 Configuration 10 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6...

Страница 15: ...2 Pin 1 Pin 5 Pin 6 Pin 7 Pin 8 J6 Figure 14 Configuration 11 Translator Schematic J2 J3 R1 50 W R2 50 W Table 14 Configuration 11 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3...

Страница 16: ...ignals VTT VCC 2 0 V in split power supply setup VTT is the system ground VCC is 2 0 V and VEE is 3 0 V or 1 3 V see Table 15 Table 15 Power Supply Levels Power Supply VCC VEE GND 5 0 V 2 0 V 3 0 V 0...

Страница 17: ...Miniature Test Point 5015 http www keyelco com SMT Compact Test Point 5016 Thru Hole Mount Compact Test Point 5005 5009 Chip Capacitor AVC Corporation 0603 0 01 mF 10 06035C103KAT2A http www avxcorp c...

Страница 18: ...fied 1 Connect a SMA connector on J1 2 Remove the 50 W chip resistor from R3 MC100EP16VSD This device has an option of varying the output swing amplitude and being driven single endedly In order to ut...

Страница 19: ...Gerber Files Top Layer Second Layer VEE and Ground Plane Third Layer VCC and Ground Plane Figure 16 Gerber Files Bottom Layer ECLinPS ECLinPS Lite ECLinPS Plus and ECLinPS MAX are trademarks of Semic...

Страница 20: ...ems or any FDA Class 3 medical devices or medical devices with a similar or equivalent classification in a foreign jurisdiction or any devices intended for implantation in the human body Should you pu...

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