ON Semiconductor AGB2N0CS-GEVK, Руководство пользователя

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AGB2N0CS − GEVK
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Jumper Pin Location
The jumpers on headboards start with Pin 1 on the
leftmost side of the pin. Grouped jumpers increase in pin
size with each jumper added.
Figure 5. Pin Locations for a Single Jumper. Pin 1 is Located at the Leftmost Side
Pins 1 − 4 Pin 1
Jumper/Header Functions & Default Positions
The P1 jumper/header configuration allows configuration
of parallel data. Its default position shorts pins 2 − 3, which
enables the parallel data buffer to pass parallel data signals.
When pins 1
− 2 are shorted, the parallel data buffer is
disabled.
AGB2N0CS − GEVK Connectors
The evaluation board supports has various different
connectors on-board, including a Demo 3 connector, two
MIPI/HiSPi connectors for the Demo 2
×
headboard, the
14-pin Demo 2
×
headboard connector, and 26-pin Demo 2
×
headboard connector.
Headboard Connectors
The Demo 2 × headboard connectors are described in the
pinouts in Tables 1 and 2. The headboard connector has a
14-pin and 26-pin connector, as well as two MIPI/HiSPi
connectors.
Baseboard Connector
The Demo 3 Baseboard connector is shown in the pinout
in Table 3. The Demo 3 connector has a serial sensor data
input, I
2
C control interface, headboard power, and parallel
image data interface.
Table 1. 26-PIN DEMO 2X HEADBOARD CONNECTOR FUNCTION DESCRIPTION (J1)
Pin Name Description DIR Comment
1 S_DATA8 Parallel Data8 I/O Parallel Data Bit
2 S_DATA9 Parallel Data9 I/O Parallel Data Bit
3 S_DATA10 Parallel Data10 I/O Parallel Data Bit
4 S_DATA11 Parallel Data11 I/O Parallel Data Bit
5 S_DATA12 Parallel Data12 I/O Parallel Data Bit
6 S_DATA13 Parallel Data13 I/O Parallel Data Bit
7 S_DATA14 Parallel Data14 I/O Parallel Data Bit
8 S_DATA15 Parallel Data15 I/O Parallel Data Bit
9 S_DATA6 Parallel Data6 I/O Parallel Data Bit
10 S_DATA7 Parallel Data7 I/O Parallel Data Bit
11 GND Ground PWR
12 GND Ground PWR
13 S_LINE_VALID Parallel Line Valid Out Check Line Valid Signal
14 S_SP5 General Control Signal 5 Out Signal @ +3.3 V Level
15 NOT USED Not Used NA
16 HEAD_RESET_L Reset Signal to Sensor In Reset to Headboard Sensor
17 S_FRAME_VALID Parallel Frame Valid Out Check Frame Valid Signal
18 HEAD_SDA I
2
C Data to Sensor I/O Signal @ +3.3 V Level
19 HEAD_SCL I
2
C Clock to Sensor I/O Signal @ +3.3 V Level
20 NOT USED Not Used NA
21 +5V0_HEAD +5V0 Power Input PWR For Powering Up the Headboard
22 +5V0_HEAD +5V0 Power Input PWR For Powering Up the Headboard
23 S_PIXCLK Parallel Pixel Clock In Parallel Data Pixel Clock
24 GND Ground PWR