Omron NYP - 1 Series, Руководство пользователя по оборудованию

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PCI Express Port
Provides BIOS Chipset details for the submenu Platform Controller Hub / PCI Express Configu-
ration / PCI Express Port.
Changeable BIOS PCI Express Port parameters and their factory default values:
Item Default / Remark
PCI Express Port Enabled
Topology
CPU specific
*1
ASPM Disabled
Gen 3 Eq Phase3 Method Software Search
UPTP 5
DPTP 7
ACS Enabled
URR Disabled
FER Disabled
NFER Disabled
CER Disabled
CTO Disabled
SEFE Disabled
SENFE Disabled
SECE Disabled
PME SCI Enabled
Hot Plug Disabled
Advanced Error Reporting Enabled
PCIe Speed Auto
Transmitter Half Swing Disabled
Detect Timeout 0
PCH PCIE
£
LTR
*2
Enabled
Snoop Latency Override Auto
Non Snoop Latency Override Auto
Force LTR Override Disabled
PCIE £ LTR Lock
*2
Disabled
Extra options Detect Non-Compliance Device Disabled
Prefetchable Memory 10
Reserved Memory Alignment 1
Prefetchable Memory Alignment 1
*1. CPU specific:
•
For 7
th
generation CPUs: Port 0, 4 = Unknown. Port 2, 3, 6 = x1.
•
For 6
th
generation CPUs: Port 0, 1, 2, 5, 6, 7 = Unknown. Port 3, 4 = x1.
*2. The default does not change but the PCIE number is port specific.
•
For 7
th
generation CPUs:
Port 0: PCIE1. Port 2: PCIE3. Port 3: PCIE4. Port 4: PCIE5. Port 6: PCIE9.
•
For 6
th
generation CPUs:
Port 0: PCIE5. Port 1: PCIE6. Port 2: PCIE7. Port 3: PCIE8. Port 4: PCIE9. Port 5: PCIE10. Port 6:
PCIE11. Port 7: PCIE12.
Appendices
A-32
NY-series Industrial Panel PC Hardware User's Manual (W555)