Omron CP1L-EL20DR-D, Руководство по эксплуатации

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Auxiliary Area Allocations by Address Appendix D
A215 00 to 07 First Cycle
Flags after
Network Com-
munications
Error Each flag will turn ON for just one
cycle after a communications error
occurs. Bits 00 to 07 correspond to
ports 0 to 7. Use the Used Communi-
cations Port Number stored in A218
to determine which flag to access.
Determine the cause of the error
according to the Communications
Port Completion Codes stored in
A203 to A210.
Note These flags are not effective
until the next cycle after the
communications instruction is
executed. Delay accessing
them for at least one cycle.
ON: First
cycle after
communica-
tions error
only
OFF: Other
status --- --- --- ---
A216
to
A217 All Network Com-
munications
Completion
Code Storage
Address The completion code for a communi-
cations instruction is automatically
stored at the address with the I/O
memory address given in these
words.
Place this address into an index reg-
ister and use indirect addressing
through the index register to read the
communications completion code. I/O memory
address for
the network
communica-
tions comple-
tion code
storage --- --- --- ---
A218 All Used Commu-
nications Port
Numbers Stores the communications port
numbers used when a communica-
tions instruction is executed using
automatic communication port allo-
cations. 0000 to 0007
hex: Commu-
nications port
0 to 7 --- --- --- ---
A219 00 to 07 Communica-
tions Port
Error Flags ON when an error occurred during
execution of a network instruction
(SEND, RECV, CMND, or PMCR).
Bits 00 to 07 correspond to commu-
nications ports 0 to 7. ON: Error
occurred
OFF: Normal
condition Retained --- --- ---
A262
and
A263 All Maximum
Cycle Time These words contain the maximum
cycle time since the start of PLC
operation. The cycle time is recorded
in 8-digit hexadecimal with the left-
most 4 digits in A263 and the right-
most 4 digits in A262. 0 to
FFFFFFFF:
0 to
429,496,729.
5 ms
(0.1-ms units) --- --- --- ---
A264
and
A265 All Present Cycle
Time These words contain the present
cycle time in 8-digit hexadecimal with
the leftmost 4 digits in A265 and the
rightmost 4 digits in A264. 0 to
FFFFFFFF:
0 to
429,496,729.
5 ms --- --- --- ---
A270
to
A271 All High-speed
Counter 0 PV Contains the PV of high-speed
counter 0. A271 contains the left-
most 4 digits and A270 contains the
rightmost 4 digits.
The PV is cleared when operation
starts. --- --- Cleared Refreshed
each cycle
during
oversee
process.
Refreshed
when
PRV(881)
instruction
is exe-
cuted. ---
A272
to
A273 All High-speed
Counter 1 PV Contains the PV of high-speed
counter 1. A273 contains the left-
most 4 digits and A272 contains the
rightmost 4 digits.
The PV is cleared when operation
starts. --- --- Cleared Refreshed
each cycle
during
oversee
process.
Refreshed
when
PRV(881)
instruction
is exe-
cuted. ---
Address Name Function Settings Status
after
mode
change
Status
at star-
tup
Write
timing
Related
flags, set-
tings
Words Bits