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Содержание OB688K1A

Страница 1: ...MC68000 SINGLE BOARD COM PUTE R USER S MANUAL 01 OMNISvTE...

Страница 2: ...ir cuit described herein neither does it convey any license under its patent rights nor the rights of others The technical information contained herein is provided for reference evaluation and repair...

Страница 3: ...5 On board Memory 10 3 5 1 On board Read Only Memory 10 3 5 2 On board Dynamic RAM 10 11 3 6 Address Decoding and Memory Mapping 11 3 6 1 ROM Address Selection SW 3 12 3 6 2 RAM Address Selection SW 1...

Страница 4: ...figuration 30 4 9 Timer K16 K17 33 4 10 External RAM Access K12 K27 34 4 11 Watchdog Timer for External RAM Access K23 35 4 12 Optional Front Panel K1 35 4 13 Miscellaneous Jumper Identification 37 4...

Страница 5: ...election 23 ROM DTACKdeiays 25 ROM DTACK delay Jumpers 25 Interrupt Jumpers 26 Bus Arbitration Jumper Configuration 28 Reset Jumper Configuration 29 ROM Size Jumper Configuration and Location 30 ROM C...

Страница 6: ......

Страница 7: ...o aJ 0 co I 0 I D _ C cn c DO mo 1 o z c i C D I 3 UJ4 b K24 K34D UJ2 K231 R19 rn 0 0 N I u 5 UJ5 C26 U60 U64...

Страница 8: ...3...

Страница 9: ...8K1A Single Board Computer from its shipping carton Save the packing material for storing and reshipping the items in case this becomes necessary 1 3 Inspection The OB68K1A Single Board Computer shoul...

Страница 10: ...erial arbitration K9 K9 2 TO K9 1 CBRQ connected to Multibus K10 K10 5 TO K10 6 Normal RTS Circuit Board Traces K10 4 TO K10 5 Serial Port transparent mode enabled K11 32K K11 1 TO K11 2 Onboard RAM b...

Страница 11: ...OARD SERIAL 1 0 PORTS On board 1 0 begins at address FFFEOO HEX See table 6 2 for specific device address assignments Serial Port 0 is configured as a modem for direct connec tion to a RS232C terminal...

Страница 12: ...ROM up to 192K bytes h Two asynchronous serial ports RS232C i Hardware or software programmable baud rate generator j Two programmable 16 bit parallel I O ports k Three 16 bit programmable timers I 1...

Страница 13: ...HOST BUS CLOCK CONST CLOCK MULTI MASTER BUS ARBITRATION EXTERNAL RAM ACCESS ARBITRATION I ADDRESS DECODING ROM PAO 7 PIA 1 PBO 7 CONTROL 1 _ _ 1 PARALLEL PORTS t PAO 7 PIA 2 PBO 7 CONTROL I TIMER IEEE...

Страница 14: ...nnectors 3 2 Timer A three channel 16 bit timer MC6840 is available on the board This timer is in tended primarily for processor housekeeping No connector is provided for input or output signals to or...

Страница 15: ...dynamic RAM chips If configured for 16Kx1 parts a total of 32K bytes are available If configured for 64Kx1 parts a total of 128K bytes are available The board is offered with either the 16K or 64K par...

Страница 16: ...to wait for the completion of an instruction The LOCK feature of Multibus is implemented so an offboard master may do a test and set operation to the onboard RAM Also see sections 3 6 2 and 3 6 4 3 6...

Страница 17: ...oundary For 128K RAM switch SW 1 selects base address on 128K byte blocks For 128K RAM BIT 1 of SW 1 is a don t care bit since pins 13 and 14 on U28 are tied together and the cut trace option at A16 i...

Страница 18: ...y space on the Multibus External access spaces of Multiple OB68K1A boards must not overlap The OB68K1A is protected from accessing its own RAM via the Multibus by negating onboard access while perform...

Страница 19: ...keep the system from hanging up if no response is received Conditions that will cause a bus error are a Access to off board memory addresses that have no responding memory not plugged in or not worki...

Страница 20: ...s removed the card uses the BCLK and CCLK generated by another master in the Multibus bin 3 9 4 The E Clock The 68000 outputs an E clock that is one tenth the processor clock frequency Synchronous tra...

Страница 21: ...or stack pointer These two vectors must be stored in PROM because the contents of RAM are unknown at restart time The OB68K1A causes the first four memory accesses following a restart to be uncon diti...

Страница 22: ...2 Future RAM Enhancement K14 2 CClK to Multibus K15 13 ACIA IRQ Handshake Configuration Test points K16 10 Timer 2 3 ClK Gate Output Timer IRQ PIA 0 IRQ s K17 4 Timer 1 ClK gate output K18 6 SW Baud...

Страница 23: ...2_UF_1 ISP13 U66 U67 1 1 _ K3 t3M Ii K33 sl K29 1 UJ7 I U41 U45 5 K21 4 rn U SP4J I 1 SP7 1 1 SP 8 1 U7 5 l U I 8 5 I U29 5 OB68K1 A OMNIBYTE CORPoRATION 0 1 82 C15 03 R15 tlg SW3 ROM I UJ8 5 1 U42 5...

Страница 24: ...wer for an in line RS232C to 20MA current loop converter The factory configuration of Ports 0 and 1 are identical to the Motorola MEX68KDM design module s serial ports including the implementa tion of...

Страница 25: ...7 U11 8 3 U12 1 8 P3 3 TXD 4 P3 5 RXD 9 U12 13 5 U11 3 10 P3 9 CTS Note P3 is PORT 1 Connector K25 PORT 0 JUMPERS 1 P4 3 RXD 11 U24 11 2 U23 1 12 P4 5 TXD 3 P4 7 RTS 13 U24 8 4 U24 6 14 P4 11 DSR 5 P4...

Страница 26: ...d Port 1 K19 is a group of 24 pins arranged in three columns as shown in Figure 4 1 2 The center row of pins connect to the baud rate setting pins of the COM8116 baud rate generator The baud rate may...

Страница 27: ...storing a value of E5 will set Port 0 for 9600 baud DCBA 1110 and Port 1 for 300 baud DCBA 0101 If one Port is selected for manual baudrate the corresponding bits of the byte written to the baudrate a...

Страница 28: ...hdog timer to an encoder that operates the BERR and HALT lines of the 68000 When K6 2 to K6 3 is installed BERR enabled and DTACK is not received from an addressed device a bus error is generated and...

Страница 29: ...tive only for on board ROM access For off board accesses DTACK is derived from the Multibus XACK signal For on board RAM accesses DTACK is derived from the RAM controller circuitry Normal onboard RAM...

Страница 30: ...K20 0 2 00 0 3 0 4 0 5 0 6 0 7 0 8 L K20 1 U51 190 ROM WAIT STATES TAP 2 U53 44 ROM WAIT STATES TAP 3 U51 1 ROM DTACK INPUT 2 3 FACTORY STANDARD K21 1 U53 3 2 ROM WAIT STATES TAP 2 U53 4 4 ROM WAIT ST...

Страница 31: ...connected to the priority encoder inputs Both the Multibus interrupts and the inputs to the priority encoder are located in jumper group K2 See Figure 4 4 Priority encoder input seven is the highest...

Страница 32: ...talled and K7 should be installed for single master or highest priori ty board in a multimaster configuration Common Bus Request CBRQ is a signal that alerts a Multibus Master that another Master need...

Страница 33: ...MPER IN SINGLE MASTER OR HIGHEST PRIORITY BOARD IN MULTIMASTER SYSTEM WITH SERIAL ARBITRATION JUMPER OUT ALL OTHER CONFIGURATIONS 1 P1 1 BREQ 2 U21 15 JUMPER IN PARALLEL ARBITRATION JUMPER OUT SERIAL...

Страница 34: ...t Pin K3 2 to both Z3 and Z4 See Figure 4 13 This modification disables the onboard reset generator and the RESET push button will not be operative The Master driv ing INIT must meet the power on timi...

Страница 35: ...OB68K1A have 28 pins This is to provide for operation with certain types of 32K and 64K ROM chips For operating with the 24 pin devices ROM s MUST be installed with the unused pins on the right side...

Страница 36: ...2716 OBK1 A K22 27128 OBK1A K22 2732 K22 oBK1AIK22 27256 K22 0 0 OBK1A K22 2764 FACTORY STANDARD 000 0 0 0 0 0 0 0 000 0 000 0 K22 88 OBK1A K22 UD USER DEFINABLE ROM CONFIGURATION PLUGS LAYOUTS FIGURE...

Страница 37: ...E CE CE 07 07 07 07 07 X X X X X 05 05 05 05 05 ex ex ex ex 04 03 03 03 03 03 PIN 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PIN 27256 27128 2764 2732 2716 Vpp Vpp Vpp Al2 Al2 Al2 AJ AJ AJ AJ AJ NJ NJ...

Страница 38: ...To use the timer as a programmable interrupt generator for the CPU no external clock or gate connections are needed The MC6840 may use the 1 MHz E clock as a time base The timer IRQ is usually connect...

Страница 39: ...ress lines A19 A23 have been pulled to logic 0 to accommodate systems that do not implement the full 16M byte address Please note that the 128K RAM starts on 128K byte boundaries even if a lesser amou...

Страница 40: ...jumper K23 See Figure 4 13 4 12 Optional Front Panel K1 Jumper group K1 is provided as a means of connecting a front panel to the OB68K1A Using the K1 signals a front panel can be implemented that in...

Страница 41: ...RUN 7 0 DPST TOGGLE 8 0 HALT SS STEP NO 10 0 C DPST MOMENTARY 9 0 NC NMI 5 7403 DPST MOMENTARY 4 RESET NO o C 2 1 6 3 GROUND 5V DPST o NC MOMENTARY 470 HALT OPTIONAL FRONT PANEL CIRCUIT FIGURE 4 12 B...

Страница 42: ...mper groups not documented elsewhere in the text are included in Figure 4 13 2 1 K41 G EJ I _____U_1_0__S U13 K6 10 U15 U14 K4 BUS CLOCK BCLK SOURCE TO MULTIBUS P1 13 NOTE IN MULTIMASTER SYSTEMS ONLY...

Страница 43: ...LTIBUS P1 31 NOTE IN MULTIMASTER SYSTEMS ONLY ONE CCLK SOURCE IS PERMITEED L U34 _5 13 12 11 10 9 8 7 6 5 4 3 2 1 K1S1 OOOOOOOOOOG B EJ I U36 1 U23 11 DTR 2 U34 24 CTS 3 U34 23 DCD 4 GND 5 TEST POINT...

Страница 44: ...LES EXTERNAL RAM ACCESS WATCHDOG TIMER CIRCUITRY P5 P4 ____I K24 1 _ 100991 K24 12V TO PORT 0 FOR EXTERNAL USE 1 12V 3 12V 2 P4 18 4 P4 20 11 _2 _1_U31_ _ S K28 CONNECTS A17 TO ONBOARD RAM ACCESS COMP...

Страница 45: ...DS PINS 3 AND 4 ON U28 ARE TIED TOGETHER THUS MAKING POSITION 1 ON SWITCH 1 A DON T CARE BIT AND REDUCES POSSIBLE ERRORS K30 01 I_U27 S o o U23 0 o o Q K31 o o K30 INVERTS SIGN OF DTR ON PORT 1 2 3 NO...

Страница 46: ...ENHANCEMENT 35 K34 P5 FOR EXTERNAL USE 8 2 0 1 5V FOR PIA 0 2 1 1 P5 22 23 IDO IK34 2 5V K35 FOR EXTERNAL USE U33 5V FOR PIA 1 1 5V 2 P5 47 48 CUT TRACE OPTIONS Z1 U25 2 555 OUTPUn Z2 U25 2 555 OUTPUn...

Страница 47: ...Group K26 cut cut cut cut Jumper Group K10 cut P3 connector Pin 11 to Pin 15 3 4 5 6 7 8 9 10 1 2 connect connect connect connect connect 3 8 4 7 6 9 K10 2 to K25 19 INTERRUPTS K2 5 to K2 13 K2 11 to...

Страница 48: ...ess Request 31 CCLK Constant Clk 32 ADR18 Bus 33 INIA Intr Acknowledge 34 ADR19 Interrupts 35 INT6 Parallel 36 INT7 Parallel 37 INT4 Interrupt 38 INT5 Interrupt 39 INT2 Requests 40 INT3 Requests 41 IN...

Страница 49: ...d Not Bussed 27 Reserved Not Bussed 28 Reserved Not Bussed 29 Reserved Not Bussed 30 Reserved Not Bussed 31 Reserved Not Bussed 32 Reserved Not Bussed 33 Reserved Not Bussed 34 Reserved Not Bussed 35...

Страница 50: ...A6 3 2 15 4 CB1 PA5 5 3 16 6 PB7 PA4 7 4 17 8 PB6 PA3 9 5 18 10 PB5 PA2 11 6 19 12 PB4 PA1 13 7 20 14 PB3 PAO 15 8 21 16 PB2 CA2 17 9 22 18 PB1 CA1 19 10 23 20 PBO NO CONN 21 11 24 22 5 VOLTS 5 VOLTS...

Страница 51: ...4 17 8 CTS 9 5 18 10 DSR 11 6 19 12 GROUND 13 7 20 14 DTR DCD 15 8 21 16 5VDC GROUND 17 9 22 18 12 VDC GROUND 19 10 23 20 12 VDC 21 11 24 22 23 12 25 24 25 13 26 ACIA CONNECTOR PORT 0 PINOUT DCE TABL...

Страница 52: ...609 5031 Berg 66167 025 Ansley 609 25P Note that these are common ribbon cable connectors and although the part numbers above are only for the Berg and T BIAnsley parts equivalent con nectors are avai...

Страница 53: ...actory standard memory configuration MAP 1 is shown in the diagrams of Figure 6 1 1 6 1 2 Switch settings for this map are SWITCH SETTING ON 0 OFF 1 SW 1 RAM BASE ADDRESS 000000 0000 0000 SW 2 I O BAS...

Страница 54: ...FElFFF f t ON BOARD ROM 64K bytes RESERVED MEMORY EXCEPTION VECTORS MACSBUG RAM MACSBUG STACK MACSBUG ROM 8K ON BOARD I O 5K FFOOOO t o f OFF BOARD NOTE I O ALL UNSPECIFIED 63 5K bytes LOCATIONS ARE...

Страница 55: ...bytes J I o ON BOARD RAM 128K bytes FFOOOO r OFF BOARD I O 63 5K bytes RESERVED MEMORY EXCEPTION VECTORS MACSBUG RAM MACSBUG STACK MACSBUG ROM 8K ON BOARD I O 5K NOTE ALL UNSPECIFIED LOCATIONS ARE OF...

Страница 56: ...OARD ROM 64K bytes 030000 OFF BOARD I O 63 5K bytes 040000 r RESERVED MEMORY EXCEPTION VECTORS MACSBUG RAM MACSBUG STACK MACSBUG ROM 8K ON BOARD I O 5K NOTE ALL UNSPECIFIED LOCATIONS ARE OFF BOARD MEM...

Страница 57: ...ON BOARD ROM 64K bytes 030000 j_ 1 OFF BOARD I O 63 5K bytes 040000 RESERVED MEMORY EXCEPTION VECTORS MACSBUG RAM MACSBUG STACK MACSBUG ROM 8K ON BOARD 1 0 5K NOTE ALL UNSPECIFIED LOCATIONS ARE OFF B...

Страница 58: ...of the I O address In Table 6 2 XX represents the upper two hexidecimal digits determined by SW 2 These switches are normally set at the factory to FF to place the 64K byte I O block at the upper end...

Страница 59: ...XFF40 R W Data Direction Reg A eRA 2 0 MC 6821 XXFF40 R W Peripheral Reg A CRA 2 1 XXFF42 R W Data Direction Reg B CRB 2 0 XXFF42 R W Peripheral Reg B CRB 2 1 XXFF44 R W Control Register A XXFF46 R W...

Страница 60: ...tained in the following important areas 1 I O Circuitry The same peripheral chips are included Two 6850 ACIA s two 6821 PIA s one 6840 three channel timer 2 Connector Pinout The pinout of both serial...

Страница 61: ...ore 16 bit words with the high and low bytes in the opposite order Intel words are stored with the least significant byte in the next higher odd location This organization was induced on Multibus memo...

Страница 62: ...DATO DJ TF H L MULTIBUS TRANSFE DEVICE BYTE BHENI ADRO DATA PATH TRANSFERRED 6 BIT DEVICE MULTIBUS 68000 CPU BOARD MC 68000 00 7 H H B BIT DATO DAT7 EVEN UDS D8 F ATO 7 I 00 7 H L 8 BIT DATO DAT7 ODD...

Страница 63: ...shown as dotted lines in these figures NOTE THE FOLLOWING INFORMATION CONTAINS VALUABLE PROPRIETARY INFOR MATION WHICH REMAINS PROPERTY OF OMNIBYTE CORPORATION AND IS COPYRIGHTED IT IS PROVIDED HERE F...

Страница 64: ...3 OB68K1A REV e 74164 i II IiI Ii 14 4 8 7 _ v V __ T _42 j_ L l J_ _ l cm f _ _f 1 _ NOTE DENOTES 5V ALL DISCRETE RESISTORS 5 TOL AL L DISCRETE CAFlICITORS 5 TeL _ _ _ _ _ _ _ _ OB68K1A SCHEMATIC CPU...

Страница 65: ...I II Ibl 12 8 JW t RS o 0025 00 De 24 01 Il2 23 D3 22 Il2 D4 2t 03 OS20 D4 D6 III OS J I 07 III D6 1 J1 07 I TXD II 0 RlCIi R W f E RS AI CSI 10 IlIQ N CSO 9ai2 iii II lIEl n I IW i I C M 3 C 15 4 II...

Страница 66: ...t t c t c 1IDb Dlr l I f 1 t DCi 013 Dlf DIIIf 1114 74 75 7G 77 78 79 80 81 5 0 tcJ NJ tc orr Il2II AI Q b A2 E 54 II 410 All C IN 1M P M te fS E E 47U1 4 I I5lI All C All E lIV lIf ClI2 A7 C C ClIO K...

Страница 67: ...6 7 OB00153LE LED RED 1 L1 OB00835LE LED YELLOW 1 1 2 OBOOO08RE 47 OHM 1 4W RESISTOR 5 R22 26 28 29 31 32 OBOO011RE 100 OHM 1 4W 1 R12 OBOO013RE 150 OHM 1 4W 1 R27 OBOO015RE 220 OHM 1 4W 2 R16 30 OBO...

Страница 68: ...PIN SIP 10 SP7 8 9 11 13 14 15 16 17 18 OB00848SP 22K OHM 6 PIN SIP 1 SP12 OB00882SP 470 OHM 10 PIN SIP 1 SP5 OB00913SP 47K OHM 10 PIN SIP 4 SP3 4 6 10 OB00163SW PUSH BUTTON SWITCH N O 1 SW5 oB00834SW...

Страница 69: ...03381C MC6821 2 U32 U33 OB003421C MC6840 1 U35 OB003471C MC6850 2 U26 U34 OB003571C MC68000L10 1 U36 OB002551C COM8116 1 U56 OB002631C DP8409 2 1 U84 OB00690lC 64K X 1DRAM 128K 16 U66 81 OB005991C 16K...

Страница 70: ...th the board It provides a vehicle to initialize and configure the on board I O devices examine the MC68000 registers and perform various other functions of this powerful monitor as listed in the comm...

Страница 71: ...RANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PUR POSE Omnibyte s liability shall be limited to the purchase price of the item or items and Omnibyte shall not be responsible or liable for any...

Страница 72: ...Serial I O Interface Cable Assy 10 long OB68K1S1C Parallel I O Interface Cable Assy 5 long OB68K1 P1C Dual In Line Shunt OB01049CN Omnibyte s terms are NET 30 DAYS with approved credit The F O B point...

Страница 73: ...her in performance and circuit complexity than has been previously available The MC68000 is the first of a family of such VLSI microprocessors from Motorola It combines state of the art technology and...

Страница 74: ...rogram Count er Relative Implied Included in the register indirect addressing modes is the capability to do postincrementing predecrementing offset ting and in dexing Program counter relative mode can...

Страница 75: ...L Logical Shift Left RTR Return and Restore BRA Branch Always LSR Logical Shift Right RTS Return from Subroutine BSET Bit Test and Set MOVE Move SBCD Subtract Decimal with Extend BSR Branch to Subrout...

Страница 76: ...e operation size When an address register is used as the destination operand the entire register is affected regardless of the operation size If the operation size is word any other operands are sign...

Страница 77: ...1 10 9 8 7 6 5 4 3 2 o MSB High Order Long Word 0 Low Order LSB Long Word 1 Long Word 2 Addresses 1 Address 32 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o MSB High Order AddressO Low Order LSB 1 2 MSB Mo...

Страница 78: ...in the address register specified by the effective address register field MEMORY ADDRESS MODES These effective address ing modes specify that the operand is in memory and provide the specific address...

Страница 79: ...nsion depending on the size of the opera tion Byte operation operand is low order byte of exten sion word Word operation operand is extension word Long word operation operand is in the two extension w...

Страница 80: ...ecrement indirect with postdecrement INTEGER ARITHMETIC OPERATIONS The arithmetic operations include the four basic opera tions of add ADD subtract SUB multiply MUll and divide DIV as well as arithmet...

Страница 81: ...ROXR 8 16 32 BIT MANIPULATION OPERATIONS Bit manipulation operations are accomplished using the ollowing instructions bit test BTST bit test and set BSET bit test and clear BCLR and bit test and chang...

Страница 82: ...TABLE 13 SYSTEM CONTROL OPERATIONS Instruction Operation Privileged RESET Reset external devices RTE Return from exception STOP Stop program execution ORI to SR Logical OR to status register MOVE USP...

Страница 83: ...lses In this case the pro cessor is trying to reset the rest of the system Therefore there is no effect on the internal state of the processor All of the processor s internal registers and the status...

Страница 84: ...m stack pointer implicitly or address register seven explicitly access the user stack pointer PRIVILEGE STATE CHANGES Once the processor is in the user state and executing instructions only exception...

Страница 85: ...tion while the bus error and reset inputs are used for access control and processor restart The internally generated exceptions come from instructions or from ad FIGURE 23 ADDRESS TRANSLATED FROM 8 BI...

Страница 86: ...p 0 reset has highest priority followed by bus error and then address er ror Within Group 1 trace has priority over external inter rupts which in turn takes priority over illegal instruction and privi...

Страница 87: ...ying the level number of the interrupt being acknowledged on the ad dress bus If external logic requests an automatic vectoring the processor internally generates a vector number which is determined b...

Страница 88: ...tack The pro gram counter and the copy of the status register are of course saved The value saved for the program counter is ad vanced by some amount two to ten bytes beyond the ad dress of the first...

Страница 89: ...ta and alterable INSTRUCTION PRE FETCH The MC68000 uses a 2 word tightly coupled instruction prefetch mechanism to enhance performance This mechanism is described in terms of the microcode opera tions...

Страница 90: ...Test a Bit bit number OF Destination Z CHK Check Register against Bounds If On 0 or On ea then TRAP U U U CLR Clear an Operand 0 Destination 0 1 0 0 CMP Compare Destination Source CMPA Compare Addres...

Страница 91: ...SET Reset External Devices ROL ROR Rotate Without Extend Destination Rotated by count Destination 0 ROXL ROXR Rotate with Extend Destination Rotated by count Destination 0 RTE Return from Exception SP...

Страница 92: ...ss calculation where indicated In Table 26 the headings have the following meanings An address register operand On data register operand ea an operand specified by an effective address and M memory ef...

Страница 93: ...12 3 0 20 312 20 3 2 20 312 24 4 2 26 4 2 24 4 2 28 5 2 An 12 3 01 12 3 01 20 312 20 312 20 3 2 24 412 26 412 24 412 28 512 An 14 3 0 14 3 01 22 312 22 312 22 3 2 26 412 28 4 2 26 412 30 512 An d 16...

Страница 94: ...e instructions The number of bus read and write cycles is shown in parenthesis as r wL The number of clock periods and the number of read and write cycles must be added respectively to those of the ef...

Страница 95: ...Long 8 1 0 12 2 0 Byte 8 111 12 2 1 BCLR Long 10 1 0 14 2 0 Byte 8 1 1 12 211 BSET Long 8 1 0 12 2 0 Byte 4 1 0 8 2 0 BTST Long 6 1 0 10 2 0 add effective address calculation time indicates maximum va...

Страница 96: ...perform the opera tions store the results and read the next instructions The number of read and write cycles is shown in parenthesis as r wl In Table 33 the headings have the following meanings Dn dat...

Страница 97: ...ROCESSING CLOCK PERIODS Exception Periods Address Error 50 4 7 Bus Error 50 417 Interrupt 44 5 3 Illegal Instruction 34 4 3 Privileged Instruction 34 4 3 Trace 34 4 3 The interrupt ac nowledge bus cyc...

Страница 98: ...ansistor Drive Peripheral Lines Program Controlled Interrupt and Interrupt Disable Capability CMOS Drive Capability on Side A Peripheral Lines Two TTL Drive Capability on All A and B Side Buffers TTL...

Страница 99: ...ent VIL 0 4 VI PAo PA7 CA2 IlL 1 3 2 4 rnA Output High Voltage ILoad 200 Al PAo PA7 PBo PB7 CA2 CB2 VOH VSS 2 4 V ILoad 10 AI PAo PA7 CA2 VCC 1 0 Output Low Voltage ILoad 3 2 mAl VOL VSS O 4 V Capacit...

Страница 100: ...rd TTL as an input the internal pullup resistor on this line represents 1 5 standard TTL loads The function of this signal line is programmed with Control Register A Peripheral Control CB2 Peripheral...

Страница 101: ...Operation on the ap propriate section Control of CA2 and CB2 Peripheral Control Lines CRA 3 CRA 4 CRA 5 CRB 3 CRB 4 and CRB 5 Bits 3 4 and 5 of the two control registers are used to control the CA2 a...

Страница 102: ...ransition as specified by bit 1 b3 1 Read Strobe with E Restore CA2 goes low on first high to Iow E transition following an MPU read of Output Register A returned high by next high to Iow E transition...

Страница 103: ...on Timer 3 Capable of 4 MHz for the MC6840 6 MHz for the MC68A4Q and 8 MHz for the MC68B40 Programmable Interrupts IRQ Output to MPU Readable Down Counter Indicates Counts to Go Until Time Out Select...

Страница 104: ...rct TOI R Gl W Tf 1 W R I G1 Before TO Comparison 1 0 1 Gl l R Gl W R 1 W R I TO Before Gl Pulse Width 1 1 0 Gl I R GlW R 1 W R I G Gf Before TO Comparison 1 1 1 Gl I R Gl W R 1 W R I G Gf Before TO G...

Страница 105: ...he active low Interrupt Request signal is normally tied directly or through priority in terrupt circuitry to the IRQ input of the MPU This is an open drain output no load device on the chip which per...

Страница 106: ...ontrol Registers are undisturbed by an Internal Reset and may be written into regardless of the state of CR 10 The least signifcant bit of Control Register 3 is used as a selector for a 8 prescaler wh...

Страница 107: ...d but prior to reading the Timer Counter An Individual Interrupt Flag is also cleared by a Write Timer Latches W command or a Counter Initialization CI sequence provided that W or CI affects the Timer...

Страница 108: ...esponse is defined in this data sheet Refer to the Programmable Timer Fundamentpls and Applications manual for a discussion of the output signals in other modes Signals appear at the outputs unless CR...

Страница 109: ...lization signal by clearing CRX4 The counter is enabled by an absence of a Timer Reset condition and a logic zero at the Gate input In the 16 bit mode the counter will decrement on the first clock cyc...

Страница 110: ...ious from the name the output returns to a low level after the initial Time Out and remains low until another Counter Initialization cycle occurs As indicated in Table 6 the intemal counting mechanism...

Страница 111: ...of the timers within the PTM may be programmed to compare the period of a pulse giving the frequency after calculations at the Gate input with the time period re quested for Counter Time Out A negati...

Страница 112: ...terface with pro per formatting and error checking The functional configuration of the ACIA is programmed via the data bus during system initialization A programmable Control Register provides variabl...

Страница 113: ...master reset is utilized The ACIA also con tains internal power on reset logic to detect the power line turn on transition and hold the chip in a reset state to pre vent erroneous output transitions p...

Страница 114: ...and a selected register is read When it is low the ACIA output drivers are turned off and the MPU writes into a selected register Therefore the Read Write signal is used to select read only or write o...

Страница 115: ...W low Writing data into the register causes the Transmit Data Register Empty bit in the Status Register to go low Data can then be transmitted If the transmitter is idling and no character is being tr...

Страница 116: ...he Receive Data Register and error logic and the peripheral modem status inputs of the ACIA Receive Data Register Full RDRF Bit 0 Receive Data Register Full indicates that received data has been trans...

Страница 117: ...number of ones is odd The parity error indication will be present as long as the data character is in the RDR If no parity is selected then both the transmitter parity generator output and the receiv...

Страница 118: ...NOTES...

Страница 119: ...d this publication Please use this form TO OMNIBYTE CORPORATION 245 West Roosevelt Road 1 5 West Chicago Illinois 60185 Attention 68KSystems Support COMMENTS Product Manual _ PLEASE PRINT NAME COMPANY...

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