G. V O L T A G E S T A B I L I Z I N G W I T H S A M P L I N G E L E M E N T
- --,
I
T 71
I
L
_ _ _ _
_J
s e r i e s
c ao
r e g u l a t o r
T 2
T I
P r i n c i p l e d r awi n g o f v o l t a g e s t a bi l i z i n g
F i g u r e
2 7
The "Sampling element" consisting of the voltage divider Rl+Pl and P90
is designed so, that the voltage over Rl + Pl becomes exactly indentical
to
the reference voltage if the output voltage has the correct value. This
implies that the voltage between the inputs of the" CV error amplifier"
Tl+T2 is zero .
Should the output voltage e. g . , decrease, a positive voltage i s applied at
Z I
+out
- out
the input of the " CV error amplifier" . This increases the base current of the
series regulator through the "OR-gate" and ''Driver amplifier" , resulting
in a lower voltage drop over "Series regulator" and the output voltage returns
to the correct value.
The "Driver amplifier" increas es the voltage and current gains to a
sufficient level to control tht Series regulator.
Tl+ T2 is a temperature compensated pair and hence should be matched.
Pl is the programming constant (K ) adjustment.
P90 is the output voltage control.
P
Referring to the circuit diagram:
Dl, D2 and R2 form a protection circuit for the CV error amplifier.
C91 is an AC feed-back, reducing ripple and noise.
P2 is the offset adjustment for Tl+T2 .
T6 together with T7 form the "OR-gate" where T7 is the CV input.
Under CV conditions the CC input of the "OR-gate" is not active as the
base of T6 is reversed bias ed.
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