OLIMEX© 2015
A20-SOM user's manual
8.2 Board revision
Remember to check the schematics and the board design files to compare the differences.
Board revision
Notable changes
A
Initial release of the board
B
1. Optimized values
2. Resolved various multiplexing issues
3. Renamed few wires properly
C
1. Major routing and layout differences with previous hardware
revisions! General hardware improvement of the board based on A20-
OLinuXino-Lime2_Rev_B's memory routing. General layout improvement.
Additional GPIO connector.
2. Added GPIO-6 connector with the following signals FMINL, FMINR,
TVIN2, TVIN3, VMIC_OUT, AXP_BACKUP, AXP_RST, AXP_PWRON, UBOOT_SEL,
VDD_RTC and GND;
3. Various value optimizations
4. Memory clock now upped to 480Mhz (from 384Mhz)
D
1. Added VGA resistor matrix
2. Minor hardware optimizations adjustments
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