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Oki MSM85C154HVS, Руководство пользователя

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MSM80C154S/83C154S/85C154HVS

4

execution from the next address after the stop address where CPU power down mode was
activated.
Each of the quasi-bidirectional ports 1, 2, and 3 can be set independently as high impedance
input ports. And the 10 k

W

 pull-up resistance for these input ports can be isolated from the

power supply (V

CC

), leaving only the 100 k

W 

pull-up resistance and thereby enabling the

quasi-bidirectional ports to be driven by devices with low drive capacity. Furthermore, the
outputs of ports, 0, 1, 2, and 3 can be switched to floating status during CPU power down
modes (PD, HPD).
Three built-in 16-bit timer/counters capable of operating in a wide range of modes enable the
CPUs to be used in many different ways. And since timer/counters 0 and 1 can be operated
by external clock during CPU power down modes (PD, HPD) where the oscillator is stopped,
these two counters can also be used in cancelling CPU power down modes.
UART based serial communication can be executed at any baud rate by carry signal from
timer/counter 1 or timer/counter 2.
If an overrun or framing error is generated during data reception, the SERR bit in the I/O
control register is set. And by testing this SERR bit, the accuracy of the data can be checked
quite easily to ensure correct serial communication.
As can be seen, these CPUs are equipped with a very comprehensive range of functions. Also
note that EASE80C51mk

II

 is available for use as the program development support system

for these CPUs.
Equipped with the MSM85C154E dedicated evachip, EASE80C51mk

II

 is capable of pro-

gram area mapping, realtime tracing, generating breaks according to accumulator contents,
and various other functions designed for accurate and efficient support of program develop-
ment of these CPUs.
With this great line-up of functions and with EASE80C51mk

II

 capable of developing

programs in a very short time, MSM80C154S/MSM83C154S/MSM85C154HVS give a highly
integrated high performance solution.

Содержание MSM85C154HVS

Страница 1: ...MSM80C154S MSM83C154S MSM85C154HVS USER S MANUAL...

Страница 2: ...rranty for the use of its products and assumes no responsibilityforanyerrorswhichmayappearinthisdocumentnor does it make a commitment to update the information contained herein OKI retains the right t...

Страница 3: ...me charts 24 1 External program memory read cycle timing chart 24 2 MOVX A Rr 24 3 MOVX Rr A 25 4 MOVX A DPTR 25 5 MOVX DPTR A 26 6 MOV direct PORT 0 1 2 3 execution 26 2 6 4 MSM83C154S fundamental op...

Страница 4: ...CC B 65 4 4 1 Outline 65 4 4 2 Special function registers 67 4 4 2 1 Timer mode register TMOD 67 4 4 2 2 Power control register PCON 68 4 4 2 3 Timer control register TCON 69 4 4 2 4 Serial port contr...

Страница 5: ...101 4 6 2 2 SBUF 103 4 6 2 3 TCLK 103 4 6 2 4 RCLK 103 4 6 2 5 SMOD 104 4 6 2 6 SERR 105 4 6 3 Operating modes 106 4 6 3 1 Mode 0 106 4 6 3 1 1 Outline 106 4 6 3 1 2 Mode 0 baud rate 106 4 6 3 1 3 Mo...

Страница 6: ...nstruction is executed after temporarily returning to the main routine from continuous interrupt processing 142 4 7 5 4 Interrupt response time chart when an IE or IP manipulating instruction is execu...

Страница 7: ...ctions 212 6 ELECTRICAL CHARACTERISTICS 6 1 Absolute Maximum Ratings 216 6 2 Operational Ranges 216 6 3 DC Characteristics 217 6 4 External Program Memory Access AC Characteristics 221 6 5 External Da...

Страница 8: ...1 INTRODUCTION...

Страница 9: ...MSM80C154S 83C154S 85C154HVS 2...

Страница 10: ...clude logical processing of the carry flag and specified bit within each register transfer between the carry flag and specified bit in certain registers transfer of specified bits between different re...

Страница 11: ...ters can also be used in cancelling CPU power down modes UART based serial communication can be executed at any baud rate by carry signal from timer counter 1 or timer counter 2 If an overrun or frami...

Страница 12: ...2 PD mode CPU and oscillation all stopped Software setting Setting I O ports to floating status possible 3 HPD mode CPU and oscillation all stopped Hardware setting Setting I O ports to floating statu...

Страница 13: ...erating voltage range 1 When operating VCC 2 2 to 6V varies according to frequency 2 When stopped VCC 2 to 6V PD or HPD mode Instruction execution cycle 1 2 byte 1 machine cycle instructions 2 Multipl...

Страница 14: ...ditional timer counter 2 An additional timer interrupt 2 An additional 8 bit timer 2 control register T2CON 0C8H An additional 8 bit I O control register IOCON 0F8H Addition of two bits bit 5 PT2 and...

Страница 15: ...MSM80C154S 83C154S 85C154HVS 8...

Страница 16: ...2 SYSTEM CONFIGURATION...

Страница 17: ...MSM80C154S 83C154S 85C154HVS 10...

Страница 18: ...P1 3 P1 4 P1 5 P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 T2 T2EX RXD TXD INT0 INT1 T0 T1 HPDI WR RD PORT 0 BUS PORT PORT 1 PORT 2 PORT 3 XTAL1 XTAL2 RE...

Страница 19: ...26 P2 5 25 P2 4 24 P2 3 23 P2 2 22 P2 1 21 P2 0 MSM80C154SRS MSM83C154SRS MSM80C154SRS MSM83C154SRS Top View 40 Pin Plastic DIP 1 P1 5 2 P1 6 3 P1 7 4 RESET 5 P3 0 RXD 6 NC 7 P3 1 TXD 8 P3 2 INT0 9 P...

Страница 20: ...32 PSEN 31 P2 7 30 P2 6 29 P2 5 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 1 P1 5 2 P1 6 3 P1 7 4 RESET 5 P3 0 RXD 6 NC 7 P3 1 TXD 8 P3 2 INT0 9 P3 3 INT1 10 P3 4 T0 11 P3 5 T1 HPDI...

Страница 21: ...ic QFJ QFJ44 P S650 1 27 44 Pin Plastic QFP DFP44 P 910 0 80 2K 44 Pin Plastic TQFP TQFP44 P 1010 0 80 K 40 Pin Ceramic Piggy Back ADIP40 C 600 2 54 MSM80C154S RS MSM83C154S XXX RS MSM80C154S JS MSM83...

Страница 22: ...nal dimensions Figure 2 3 MSM80C154S MSM83C154S external dimensions MSM80C154SRS MSM83C154SRS 40 pin Plastic DIP DIP40 P 600 2 54 MSM80C154SJS MSM83C154SJS 44 Pin Plastic QFJ QFJ44 P S650 1 27 MSM80C1...

Страница 23: ...MSM80C154S 83C154S 85C154HVS 16 MSM80C154STS MSM83C154STS 44 Pin Plastic TQFP TQFP44 P 1010 0 80 K...

Страница 24: ...5C154HVS pin layout of bottom side is the same as the pin layout for MSM83C154SRS The 27C64 128 device should be used for EPROM M85C154H OKI JAPAN XXXX 2764 27128 Pin 1 for 2764 27128 Figure 2 4 MSM85...

Страница 25: ...A RESET PORT 1 P1 0 P1 7 PORT 3 P3 0 P3 7 TL1 TH0 TL0 TMOD TCON IE IP SCON TIMER COUNTER 0 1 INTERRUPT SERIAL IO SBUF T SBUF R T2CON TL2 TIMER COUNTER 2 PCH TH2 RCAP 2L RCAP 2H PCL PCHL PCLL R W AMP R...

Страница 26: ...NTER 0 1 INTERRUPT SERIAL IO SBUF T SBUF R T2CON TL2 TIMER COUNTER 2 PCH TH2 RCAP 2L RCAP 2H PCL PCHL PCLL R W AMP 256WORD 8bit RAMDP PSW ACC TR2 TR1 BR ALU IR AIR C ROM SPECIAL FUNCTION REGISTER ADDR...

Страница 27: ...1 INTERRUPT SERIAL IO SBUF T SBUF R T2CON TL2 TIMER COUNTER 2 PCH TH2 RCAP 2L RCAP 2H PCL PCHL PCLL R W AMP 256WORD 8bit RAMDP PSW ACC TR2 TR1 BR ALU IR AIR C ROM SPECIAL FUNCTION REGISTER ADDRESS DE...

Страница 28: ...2 fundamental clock pulses 1 byte 1 machine cycle and 2 byte 1 machine cycle instructions are fetched into the instruction register during M1 S1 decoded during M1 S2 and executed during M1 S3 thru M1...

Страница 29: ...H PCH PCH DATA STABLE DATA STABLE PORT OLD DATA PORT NEW DATA Instruction decoding Instruction excecution PC 1 PC 1 TM 1 Instruction decoding Instruction excecution PC 1 TM 1 TM 1 Instruction decoding...

Страница 30: ...when an instruction or data is fetched The PSEN signal is valid when at 0 level and external program data is enabled when in this valid state Although two PSEN signal outputs are obtained in a single...

Страница 31: ...L OUT INST IN PCL OUT INST IN PCL OUT INST IN INST IN S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 PCL OUT INST IN PCH OUT PCH OUT PORT 2 LATCH DATA OUT XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 2 1...

Страница 32: ...1 0 PCH OUT Rr OUT ACC DATA OUT PCL OUT INST IN WR 1 0 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 PCL OUT INST IN PCH OUT PCH OUT DPH OUT XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 2 1 0 PCH OUT DP...

Страница 33: ...0 PORT 2 1 0 PCH OUT DPL OUT ACC DATA OUT PCL OUT INST IN WR 1 0 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 2 3 PIN DATA 1 0 CPU DATA SAMPLED 1 0 PIN DATA STABLE...

Страница 34: ...1 0 PORT 2 LATCH DATA OUT RAM DATA IN S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 PORT 0 LATCH DATA XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 2 1 0 Rr OUT ACC DATA OUT FLOATING WR 1 0 PORT 2 LATCH D...

Страница 35: ...AM DATA IN PORT 2 LATCH DATA OUT DPH OUT PORT 2 LATCH DATA OUT S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 PORT 2 LATCH DATA OUT DPH OUT PORT 2 LATCH DATA OUT S1 PORT 0 LATCH DATA XTAL1 1 0 ALE 1 0 PSEN...

Страница 36: ...S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 2 3 PIN DATA 1 0 CPU DATA SAMPLED 1 0 PIN DATA STABLE Figure 2 20 MSM83C154S MOV direct PORT 0 1 2 3 execution 5 MOV dire...

Страница 37: ...n instruction register AIR and register manipulation decoder PLA for data addresses and bit addresses OperationcodesarepassedtotheIR anddataandbitaddressesarepassedtotheAIR CPU control signals are for...

Страница 38: ...t data from one or two data sources the ALU processes that data in accordance with control signals from the PLA The ALU is capable of executing the following processes Additions and subtractions with...

Страница 39: ...INTERNAL ROM 16KWORD 8BIT CPU INTERNAL DATA BUS EXTERNAL ROM MODE ENABLE ROM CPU INTERNAL DATA BUS Figure 2 23 MSM80C154S MSM83C154S program ounter This program counter is a binary up counter which i...

Страница 40: ...ess 0 thru address 16383 External instructions are executed when the address is greater than 16383 The program area is outlined in Figure 2 24 and a diagram of ROM connections made when external instr...

Страница 41: ...LATCH P0 0 P0 1 P0 2 P0 3 P0 4 P0 5 P0 6 P0 7 ALE P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 PSEN MSM80C154S MSM83C154S A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 OUTPUT ENABLE CS Q7 Q6 Q5 Q4...

Страница 42: ...s used when external data memory contents are transferred to the accumulator The external data memory connection diagram is shown in Figure 2 26 and the external data memory access time chart is shown...

Страница 43: ...3 LATCH P0 0 P0 1 P0 2 P0 3 P0 4 P0 5 P0 6 P0 7 ALE P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 RD MSM80C154S MSM83C154S A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CS R W 7 6 5 4 3 2 1 0 ROM 64...

Страница 44: ...H PCH PCH XTAL1 1 0 ALE 1 0 PSEN 1 0 WR 1 0 PORT 0 1 0 PORT 2 1 0 S6 PCL MOVX DPTR A S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 PCL PCL PCL PCL PCL PCL DPL INS...

Страница 45: ...connection diagram is shown in Figure 2 28 and the external data memory access time chart is shown in Figure 2 29 When the indirect register external memory instruction is executed the CPU passes the...

Страница 46: ...Q3 Q4 Q5 Q6 Q7 MSM74HC373 LATCH P0 0 P0 1 P0 2 P0 3 P0 4 P0 5 P0 6 P0 7 ALE RD MSM80C154S MSM83C154S A0 A1 A2 A3 A4 A5 A6 A7 CS R W 7 6 5 4 3 2 1 0 ROM 256W 8BIT I O WR Figure 2 28 Connection circuit...

Страница 47: ...CH PCH PCH XTAL1 1 0 ALE 1 0 PSEN 1 0 WR 1 0 PORT 0 1 0 PORT 2 1 0 S6 PCL MOVX Rr A S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 PCL PCL PCL PCL PCL PCL Rr INSTR...

Страница 48: ...3 CONTROL...

Страница 49: ...MSM80C154S 83C154S 85C154HVS 42...

Страница 50: ...83C154S devices If an external clock is applied to XTAL1 the input should be at 50 duty and C MOS level IDLE MODE PD HPD MODE CPU CONTROL CLOCK TIMER S I O INTERRUPT 1M XTAL1 XTAL2 XTAL C C MSM80C154S...

Страница 51: ...he capacity of the compensating capacitor depends on the ceramic resonator The XTAL1 2 frequency depends on VCC Figure 3 2 Ceramic resonator connection diagram IDLE MODE PD HPD MODE CPU CONTROL CLOCK...

Страница 52: ...registers are then initialized set to 0 two machine cycles after the XTAL1 2 oscillator commences regular operation When the reset is released instruction execution is started in the third machine cy...

Страница 53: ...M1 or M2 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 PORT DATA XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 RESET 1 0 PORT DATA PORT DATA PORT DATA CPU RES...

Страница 54: ...2 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 RESET 1 0 CPU RESET CONTROL 1 0 RESET EXCECUTE 1 0 PORT DATA 1 P...

Страница 55: ...2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 RESET 1 0 CPU RESET CONTROL 1 0 RESET EXCECUTE 1 0 F...

Страница 56: ...S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 RESET 1 0 CPU RESET CONTROL 1 0 RESET EXCECUTE 1 0 PORT DATA 1 S6 FLOATING...

Страница 57: ...in the CPU reset control circuit resulting in the reset operation being started by the CPU The CPU reset state is released when the 1 level on the RESET pin is changed to 0 An input signal level belo...

Страница 58: ...he CPU is then reset after normal XTAL1 2 oscillation has resumed The internal CPU status when the CPU is reset is shown in Table 3 1 Table 3 1 MSM80C154S MSM83C154S reset internal status Register Nam...

Страница 59: ...ction is to be executed 1 Internal ROM mode If the EA pin is connected to VCC and a 1 reset signal is applied to the RESET pin to reset the CPU an internal program memory ROM is executed from address...

Страница 60: ...4 INTERNAL SPECIFICATIONS...

Страница 61: ...MSM80C154S 83C154S 85C154HVS 54...

Страница 62: ...esses consist of eight bits and range from 00 to 0FFH in binary which correspond to 0 thru 255 in decimal All data memory RAM and special function registers ACC B TCON P0 exist in these 256 locations...

Страница 63: ...208 0D0H 205 0CDH 204 0CCH 203 0CBH 202 0CAH 200 0C8H 184 0B8H 176 0B0H 168 0A8H 160 0A0H 153 99H 152 98H 144 90H 141 8DH 140 8CH 139 8BH 138 8AH 137 89H 136 88H 135 87H 131 83H 130 82H 129 81H 128 8...

Страница 64: ...edatamemoryaddressrangefrom00to7FHisanareawheredataaddressingispossible 8 bit data manipulations can be handled directly by data address manipulation instructions The data memory address range from 80...

Страница 65: ...39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 20H 1FH 18H 17H 10H 0FH 0...

Страница 66: ...D7 D6 D5 D4 D3 D2 D1 D0 R0 01 1 D7 D6 D5 D4 D3 D2 D1 D0 R1 02 2 D7 D6 D5 D4 D3 D2 D1 D0 R2 03 3 D7 D6 D5 D4 D3 D2 D1 D0 R3 04 4 D7 D6 D5 D4 D3 D2 D1 D0 R4 05 5 D7 D6 D5 D4 D3 D2 D1 D0 R5 06 6 D7 D6 D...

Страница 67: ...ed in the stack when the stack pointer contents are 7FH and the status where accumulator contents are pushed during interrupt routine and are subsequently saved in the stack are shown in Table 4 2 The...

Страница 68: ...r data is 0 and register 1 is specified when the data is 1 When this instruction is executed register data is read from the specified register 0 or 1 and the read out register data is written into the...

Страница 69: ...register designation combinations When this instruction is executed one of the registers R0 thru R7 from the register group specified by the PSW RS0 and RS1 bank data is specified The contents of the...

Страница 70: ...any one of eight bits to be specified The bit designation combinations are listed in able 4 4 The data memory is addressed by bits b3 b4 b5 b6 and b7 of byte 2 with b7 being 0 These bits can be expres...

Страница 71: ...1 1 Table 4 5 Addressing combination table b7 b6 b5 b4 b3 RAM address 0 0 0 0 0 0 20H 32 1 0 0 0 0 1 21H 33 2 0 0 0 1 0 22H 34 3 0 0 0 1 1 23H 35 4 0 0 1 0 0 24H 36 5 0 0 1 0 1 25H 37 6 0 0 1 1 0 26H...

Страница 72: ...a addressing 13 registers P0 P1 P2 P3 TCON T2CON SCON IE IP PSW ACC B and IOCON can be specified by bit addressing If a register which does not exist at the data address is accessed when a special fun...

Страница 73: ...6 A5 A4 A3 A2 A1 A0 9F 9E 9D 9C 9B 9A 99 98 97 96 95 94 93 92 91 90 8F 8E 8D 8C 8B 8A 89 88 87 86 85 84 83 82 81 80 IOCON B ACC PSW TH2 TL2 RCAP2H RCAP2L T2CON IP P3 IE P2 SBUF SCON P1 TH1 TH0 TL1 TL0...

Страница 74: ...this bit is 0 the TR0 bit of TCON timer control register is used to control the start and stop of timer counter 0 counting If this bit is 1 timer counter 0 starts counting when both the TR0 bit of TCO...

Страница 75: ...hether the interrupt is a normal interrupt or a PD mode release interrupt Reserved bit The output data is 1 if the bit is read Bit used to specify cancellation of CPU power down mode IDLE or PD by int...

Страница 76: ...and in trigger detect mode when 1 Interrupt request flag for external interrupt 1 Bit is reset automatically when interrupt is serviced Bit can be set and reset by software when IT1 1 Counting start...

Страница 77: ...y software during interrupt service routine This flag is set after the eighth bit of data has been sent when in mode 0 or after the last bit of data has been sent when in any other mode The ninth bit...

Страница 78: ...en bit is 1 Interrupt control bit for external interrupt 1 Interrupt disabled when bit is 0 Interrupt enabled when bit is 1 Interrupt control bit for timer interrupt 1 Interrupt disabled when bit is 0...

Страница 79: ...external interrupt 1 Priority is assigned when bit is 1 Interrupt priority bit for timer interrupt 1 Priority is assigned when bit is 1 Interrupt priority bit for serial port Priority is assigned whe...

Страница 80: ...tion The flag is also set to 1 if the resultant product of a multiplication instruction MUL AB is greater than 0FFH but is reset to 0 if the product is less than or equal to 0FFH RAM register bank swi...

Страница 81: ...t port when this bit is 1 Port 2 becomes a high impedance input port when this bit is 1 Port 3 becomes a high impedance input port when this bit is 1 The 10 kohm pull up resistance for ports 1 2 and 3...

Страница 82: ...circuit drive clock control bit Timer counter 2 is switched to baud rate generator mode when this bit is 1 and the timer counter 2 carry signal becomes the serial Port transmit clock Note however that...

Страница 83: ...l modes for a wide range of applications Note that counting is stopped when XTAL1 2 are stopped 4 5 2 Timer counters 0 and 1 4 5 2 1 Outline Timer counters 0 and 1 are both equipped with a 16 bit bina...

Страница 84: ...d 1 TIMER 1 GATE C T M1 M0 GATE C T M1 M0 7 6 5 4 3 2 1 0 TIMER MODE REGISTER TMOD TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 7 6 5 4 3 2 1 0 TIMER CONTROL REGISTER TCON TIMER 0 DETECTOR T1 PIN PORT 3 5 DATA INT...

Страница 85: ...lock is passed to the timer counter when the C T bit is 0 This internal clock is the result of dividing XTAL1 2 by 12 The S3 timing signal see Figure 2 9 becomes the clock The external clock is applie...

Страница 86: ...with the S3 timing signal to form the timer counter clock signal which then serves as theF Flresetsignal TheresetF Flthenwaitsforthenextexternalclock The 0 and 1 signal cycle widths of the respective...

Страница 87: ...fbits3and7inthetimermoderegister TMOD 89H indicated in Table 4 9 Timer counter 0 is controlled by the bit 3 GATE bit When the GATE bit is 0 counting is started and stopped only by TR0 When the GATE bi...

Страница 88: ...S5 INT0 or INT1 GATE TR0 or TR1 T0 or T1 C T Figure 4 10 INT0 and INT1 timer counter start stop control circuit Table 4 10 GATE INT TR timer counter control tables GATE TR0 INT0 RUN STOP TIMER 0 0 0...

Страница 89: ...0 Bit Flag Set 7 6 5 4 3 2 1 0 GATE C T M1 M0 GATE C T M1 M0 4 5 2 5 2 Mode 0 M1 M0 0 0 In mode 0 timer counters 0 and 1 both become 13 bit timer counters by the circuit connection shown in Figures 4...

Страница 90: ...S5 Q TR0 T0 PIN PORT 3 4 Q0 Q4 TL0 5BITS Q0 Q7 TH0 8BITS C DETECTOR TF0 Figure 4 11 Timer counter 0 mode 0 DETECTOR XTAL 1 12 S3 GATE C T DATA INT1 PIN PORT 3 3 LATCH S5 Q TR1 T1 PIN PORT 3 5 Q0 Q4 T...

Страница 91: ...13 and 4 14 TL0 and TL1 in timer counters 0 and 1 serve as the counter for the eight lower bits and TH0 and TH1 serve as the counter for the eight upper bits TL0 is set by the timer counter 0 carry s...

Страница 92: ...H S5 Q TR0 T0 PIN PORT 3 4 Q0 Q7 TL0 8BITS Q0 Q7 TH0 8BITS C DETECTOR TF0 Figure 4 13 Timer counter 0 model DETECTOR XTAL 1 12 S3 GATE C T DATA INT1 PIN PORT 3 3 LATCH S5 Q TR1 T1 PIN PORT 3 5 Q0 Q7 T...

Страница 93: ...it auto reloader section and TL0 and TL1 serve as the timer counter section If a carry signal is generated by the 8 bit timer counter TL0 and TL1 the respective auto reloader register data is preset i...

Страница 94: ...PIN PORT 3 4 Q0 Q7 TL0 8BITS C DETECTOR TF0 Q0 Q7 TH0 8BITS RELOAD DATA Figure 4 15 Timer counter 0 mode 2 DETECTOR XTAL 1 12 S3 GATE C T DATA INT1 PIN PORT 3 3 LATCH S5 Q TR1 T1 PIN PORT 3 5 Q0 Q7 T...

Страница 95: ...lled only by TR1 and the control only covers count starting and stopping TF1 is set by a carry signal generated by TH0 When timer counter 0 is set to mode 3 timer counter 1 can operate in modes 0 1 or...

Страница 96: ...r preset data values are set in timer counters 0 and 1 and a counter clock designation is set in bit 2 C T of the timer mode register TMOD 89H If 1 is then set in bit 6 T32 of the 1 0 control register...

Страница 97: ...cremented by 1 In addition Q of F F1 is set on the trailing edge of T0 or T1 Thus the counter is incremented by additional 1 The same event occurs not only by the external interrupt but also by the ov...

Страница 98: ...software power down mode can not be set Example Timer 0 is in mode 1 of external clock Content of timer 0 is FF Interrupt by timer 0 is enabled TO pin is 1 If the above conditions all are established...

Страница 99: ...0 and CP RL2 1 The timer counter 2 contents are passed to the capture register RCAP2L RCAP2H when the level o the signal applied to the T2EX pin bit 1 of port 1 is changed from 1 to 0 with EXEN2 1 16...

Страница 100: ...4 14 Timer counter 2 modes RCLK TCLK CP RL2 TR2 0 0 0 1 0 0 1 1 RCLK TCLK 1 1 0 Mode 16 bit auto reload 16 bit capture Baud rate generator All operations stopped 4 5 3 3 1 16 bit auto reload mode 16 b...

Страница 101: ...and CP RL2 1 Timer counter 2 operates in the following way when 16 bit capture mode is set When the signal applied to the T2EX pin bit 1 of port 1 is changed from level 1 to 0 the TL2 and TH2 count c...

Страница 102: ...2 and TH2 and the timer counter commences to count from that preset value The carry signal is passed to a serial port The timer counter 2 carry signal activates the serial port receive circuit when RC...

Страница 103: ...8 BIT C RCAP2L Q0 Q7 TH2 8 BIT C RCAP2H DETECTOR T2EX PORT 1 1 TR2 EXEN2 DETECTOR EXF2 TIMER 2 INTERRUPT RCLK TCLK 1 CP RL2 C T2 RCLK TCLK 2 TIMER 1 OVERFLOW SMOD PCON bit 7 16 RX CLOCK MODE1 3 16 TX...

Страница 104: ...Q D L Q D R F F1 F F2 S5 T2 PORT 1 0 VCC RESET TIMER COUNTER 2 CLOCK 1 0 12T 12T S3 Figure 4 23 Timer counter 2 external clock detector circuit 4 5 3 4 2 T2EX timer counter 2 external flag input dete...

Страница 105: ...d The flag is set at M2 S1 during execution of the next instruction If a timer carry is generated during M1 thru M3 when executing a 4 machine cycle instruction the timer flag is set during M3 or M4 S...

Страница 106: ...ut clock UART mode Independent transmitter and receiver circuits for full duplex communication Double buffer in receiver circuit to provide a 1 frame time margin in processing received data Selection...

Страница 107: ...7 T2CON 4 T2CON 5 IOCON 5 SBUF R INPUT SHIFT REGISTER SBUF T MULTIPLEXER RXD P3 0 MULTIPLEXER TXD P3 1 SHIFT CLOCK INTERNAL BUS TIMER COUNTER1 OVERFLOW TIMER COUNTER2 OVERFLOW 1 2OSC Note Internal bus...

Страница 108: ...operation modes and enabling disabling data reception storage bits for the ninth data bit transmitted and received during 11 bit frame UART mode and the serial port status flag In addition to specifyi...

Страница 109: ...of the data to be sent during 11 bit frame UART mode mode 2 or 3 Receive enable bit Reception is not activated if REN is not set If SM2 is set when in 11 bit frame UART mode mode 2 or 3 and the 9th bi...

Страница 110: ...thetransmittingcircuitwheninmode 1 or 3 The timer counter 2 overflow becomes the transmitting circuit baud rate clock source when TCLK is set in mode 1 or 3 And the timer counter 1 overflow becomes th...

Страница 111: ...ing baud rate If SMOD is cleared in mode 2 1 2 OSC oscillator frequency divided by 2 divided by 2 becomes the baud rate clock source And if SMOD is set 1 2 OSC becomes the baud rate clock source SMOD...

Страница 112: ...de Notethatanoverrunerror is only detected when the data reception conditions set by SM2 have been satisfied Although the SERR flag is set by hardware when a framing or overrun error is generated it i...

Страница 113: ...first Two states after commencing the LSB output output of the TXD synchronized clock is commenced This synchronized clock is at level 0 from the latter half of S3 thru to the first halfofS6 andat 1 l...

Страница 114: ...INTERNAL SPECIFICATIONS 107 SBUF R INPUT SHIFT REG INTERNAL BUS RI SBUF T START START INTERNAL BUS TI REN SHIFT CLOCK ENABLE TXD RXD WRITE TO SBUF SERIAL PORT INTERRUPT Figure 4 28 Serial port mode 0...

Страница 115: ...D2 D3 D4 D5 D6 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 WRITE TO SCON REN RI TXD ALE S4 S5 S6 S1 S2 S3 TERMINATE TRANSMISSION RI S...

Страница 116: ...ATIONS 109 Figure 4 30 Serial port mode 0 timing and corresponding basic MSM80C154S MSM83C154S timing XTAL1 ALE OUTPUT READ RXD INPUT TXD SHIFT CLOCK RXD DATA OUTPUT S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S...

Страница 117: ...2 1 SMOD 0 B fTC1 SMOD 1 16 1 16 1 where B is the baud rate and fTC1 is the timer counter 1 overflow frequency When timer counter 1 is used as a timer internal clock in auto reload mode mode 2 the bau...

Страница 118: ...beginning of the start bit for commence ment of reception When this 1 to 0 RXD change is detected the hexadecimal counter which had been stopped in reset status commences to count up When the hexadec...

Страница 119: ...e SERR flag is set at the first M1 S3 after the hexadecimal counter has reached state 10 Note that the previous SBUF R data is preserved Conditions 1 RI 1 2 SM2 0 or SM2 1 and sampled stop bit 1 And i...

Страница 120: ...BUF T START START INTERNAL BUS TI RXD SAMPLE LOGIC 1 16 COUTER TXD RXD WRITE TO SBUF SERIAL PORT INTERRUPT REN SM2 RECEIVE DATA NEGLECT LOGIC SERR BAUD RATE CLOCK RCLK RCLK 1 RCLK 0 1 16 COUTER BAUD R...

Страница 121: ...1 timing chart D1 WRITE TO SBUF TXD TERMINATE TRANSMISSION TX CLOCK TI D2 D3 D4 D5 D6 RX COUNTER RUN RXD SAMPLE CLOCK LOAD SBUF RXD SHIFT IN CLOCK RI or SERR SET TERMINATE RECEPTION STOP BIT STOP BIT...

Страница 122: ...s used as the clock Transmission is commenced when transmit data is written in SBUF The start bit the eight SBUF data bits with the LSB first TB8 and the stop bit are transmitted sequentially from the...

Страница 123: ...ti purpose data bit 1 If the above conditions are not satisfied when the hexadecimal counter is in state 10 during the multi purpose data bit interval the received data is disregarded the SBUF RB8 and...

Страница 124: ...RI START START SBUF T INTERNAL BUS TI RXD SAMPLE LOGIC 1 16 COUTER TXD RXD WRITE TO SBUF SERIAL PORT INTERRUPT REN SM2 RECEIVE DATA NEGLECT LOGIC SERR BAUD RATE CLOCK 1 16 COUTER BAUD RATE CLOCK SMOD...

Страница 125: ...ANSMISSION TX CLOCK TI D2 D3 D4 D5 D6 RX COUNTER RUN RXD SAMPLE CLOCK LOAD SBUF RXD SHIFT IN CLOCK RI or SERR SET TERMINATE RECEPTION STOP BIT STOP BIT M1 S3 TBB D0 D1 D2 D3 D4 D5 D6 RBB D0 M1 S3 STAR...

Страница 126: ...ow baud rate is determined by the overflow frequency and SMOD value according to the following equations B fTC1 2 1 SMOD 0 B fTC1 SMOD 1 16 1 16 1 Where B is the baud rate and fTC1 is the timer counte...

Страница 127: ...re timer counter 1 must be set so that the period of a single round of the hexadecimal counter is equal to the reception data baud rate The RXD change from 1 to 0 is regarded as the beginning of the s...

Страница 128: ...tions are satisfied when the hexadecimal counter is in state 10 during reception of a multi purpose data bit it is assumed that new data is received before processing of the previously received data h...

Страница 129: ...S TI RXD SAMPLE LOGIC 1 16 COUTER TXD RXD WRITE TO SBUF SERIAL PORT INTERRUPT REN SM2 RECEIVE DATA NEGLECT LOGIC SERR BAUD RATE CLOCK RCLK RCLK 1 RCLK 0 1 16 COUTER BAUD RATE CLOCK TCLK TCLK 1 TCLK 0...

Страница 130: ...SMISSION TX CLOCK TI D2 D3 D4 D5 D6 RX COUNTER RUN RXD SAMPLE CLOCK LOAD SBUF RXD SHIFT IN CLOCK RI or SERR SET TERMINATE RECEPTION STOP BIT STOP BIT M1 S3 TBB D0 D1 D2 D3 D4 D5 D6 RBB D0 M1 S3 START...

Страница 131: ...e is shown in Figure 4 37 and the corresponding timing chart is shown in Figure 4 38 FollowingoutputofthelatchpulsefromPX X REN 1 andR1 0 aresetforshiftinof74LS1 65 data MSM80C154S MSM83C154S PX X RXD...

Страница 132: ...changed from 0 to 1 and the parallel input is latched This is then followed by REN 1 and RI 0 settings and shift in of 74LS165 data INPUT CONTROL is returned to 0 after the input has been completed S...

Страница 133: ...ONTROL PX X INPUT CONTROL RXD TXD 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 8D 7D 6D 5D 4D 3D 2D 1D OC G 74LS373 QHQGQF QEQDQCQBQA CLK CK 74LS164 B A QH H G F E D C B A INHIBIT CK 74LS165 CLOCK SERIAL IN SHIFT LOAD INP...

Страница 134: ...INPUT CONTROL INPUT OUTPUT 74LS165 OUTPUT MSM80C154S MSM83C154S OUTPUT In all examples additional multiple bit I O extension is made possible by multiple cascade connections of 74LS164 or 74LS165 Figu...

Страница 135: ...nerates address data which ensures that data bit 9 the multi purpose data bit is 1 3 At this stage all slave processors generate interrupts and check whether the received address data has specified it...

Страница 136: ...rity register IP When the relevant interrupt conditions are met the respective interrupt address is called and the interrupt routine is commenced The interrupt addresses are listed in Table 4 18 and t...

Страница 137: ...3 PI NI EX0 IE 0 PS IP 4 PI NI EX0 IE 0 PT2 IP 5 PI NI EX0 IE 0 EA IE 7 VCC PCT IP 7 VCC RETI GLOBAL ENABLE TCON 7 TF1 TIMER INTERRUPT 1 TCON 3 IE1 EXTERNAL INTERRUPT 1 TCON 5 TF0 TIMER INTERRUPT 0 TC...

Страница 138: ...5 4 3 2 1 0 EA ET2 ES ET1 EX1 ET0 EX0 Bit Flag EX0 External interrupt 0 control bit Interrupt enabled when 1 disabled when 0 ET0 Timer interrupt 0 control bit Interrupt enabled when 1 disabled when 0...

Страница 139: ...utine set the desired interrupt enable bit in the interrupt enable register IE 0A8H The desired interruptroutineisprocessedwhentheconditionsforthatroutinearemet Multi levelinterrupt processing can thu...

Страница 140: ...famain routine program is outlined in Figure 4 45 below This diagram shows the flow chart up to the point of return to the main routine NI Start of non priority interrput Start of non priority interrp...

Страница 141: ...routine have to be generated duringtheprocessingofaninterruptroutine setthedesiredinterruptenablebitintheinterrupt enable register IE 0A8H to commence the new interrupt routine Multi level interrupt p...

Страница 142: ...t 0 and the interrupt routine with lowest priority is timer interrupt 2 The interrupt level when all priority bits are 0 is 1 level and even if the interrupt conditions for an external interrupt 0 hig...

Страница 143: ...s 0 and 1 are level detected by the equivalent circuit shown in Figure 4 47 When the level of the external interrupt pin is 0 at S5 timing the level is latched and the Q output becomes 1 The latched e...

Страница 144: ...ect to digital differentiation until the S3 timing signal The RS F F in the next stage is set by the differentiated output signal The external interrupt signal applied to the RS F F is synchronized wi...

Страница 145: ...tisfied during execution of ordinary instructions in main routine If interrupt conditions are satisfied during execution of an ordinary instruction which does not manipulate IE or IP in the main routi...

Страница 146: ...3 S4 S5 S6 Instruction execution S6 1 0 1 0 M1 M4 M1 or M2 M1 M4 M1 or M2 M1 M2 1 0 Execution of one instruction Execution of one instruction Timer 1 interrput address call Figure 4 49 lnterrupt respo...

Страница 147: ...rcuit in the next cycle follow ing completion of the register manipulation instruction If interrupt conditions were met as a result of the re interrupt mask the interrupt address is called in the next...

Страница 148: ...ction execution S6 1 0 1 0 M1 or M2 M1 M4 M1 or M2 M1 M2 1 0 Execution of IE or IP manipulation instruction Execution of one instruction Timer 1 interrput address call Figure 4 50 Interrupt response t...

Страница 149: ...e following execution of the interrupt routine end instruction RETI and if the next interrupt conditions have been met during execution of a previous interrupt routine the MSM80C154S MSM83C154S calls...

Страница 150: ...turning to main routine during continuous interrupt processing S4 S5 S6 S1 S2 S3 XTAL1 ALE Timer flag 1 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 Instruction execution S6 1 0 1 0 M2 M1 M4...

Страница 151: ...n to the main routine where an instruction which manipulates the interrupt enable register IE or interrupt priority register IP is executed the MSM80C154S MSM83C154S activates the interrupt mask circu...

Страница 152: ...o main routine during continuous interrupt processing S4 S5 S6 S1 S2 S3 XTAL1 ALE Timer flag 1 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 Instruction execution S6 1 0 1 0 M2 M1 or M2 M1 1 0...

Страница 153: ...be released CPU start up by CPU resetting interrupt generation and interrupt source signal generation Execution can be recommenced from address 0 resumed from the interrupt address or from the next ad...

Страница 154: ...INTERNAL SPECIFICATIONS 147 XTAL 2 XTAL 1 TIMER S I O INTERRUPT CPU CONTROL CLOCK Bit Set SMOD HPD RPD GF1 GF0 PD IDL 7 6 5 4 3 2 1 0 PCON 87H CONTROL Figure 4 53 ldle mode equivalent circuit...

Страница 155: ...put Port data output P3 6 WR Port data output Port data output P3 7 RD Port data output Port data output XTAL 2 Oscillator operative Oscillator operative XTAL 1 Oscillator operative Oscillator operati...

Страница 156: ...ternal ROM mode S1 S2 S3 S4 S5 S6 M1 or M2 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 W PCON 1 0 PCON bit 0 1...

Страница 157: ...al ROM mode S1 S2 S3 S4 S5 S6 M1 or M2 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 W PCON 1 0 PCON bit 0 1 0 I...

Страница 158: ...the mode can be cancelled by external interrupt 0 or 1 and the INT0 or INT1 pin is set to 0 either level input or edge input 2 If trying to set the software power down mode under the conditions that t...

Страница 159: ...152 XTAL 2 XTAL 1 CPU CLOCK Bit Set SMOD HPD RPD GF1 GF0 PD IDL 7 6 5 4 3 2 1 0 CONTROL PCON 87H IOCON 0F8H I O FLOATING Bit Set T32 SERR IZC P3HZ P2HZ P1HZ ALF 7 6 5 4 3 2 1 0 Figure 4 56 Soft power...

Страница 160: ...RESET S6 M END PCON5 RPD PDRESET S5 Figure 4 57 Power down cancellation circuit at INTERRUPT level input S4 S2 S3 Q S LR IE0 or 1 PCON5 RPD PDRESET D Q D L S3 D L S5 Q PD INT0 or INT1 W TCON BUS RESET...

Страница 161: ...MSM80C154S 83C154S 85C154HVS 154 S3 Q D L Q D R F F1 F F2 S5 T0 or T1 VCC RESET PD F F1 F F2 PCON5 RPD Q S R TF0 or 1 PDRESET RESET TIMER0 1 C Figure 4 59 TIMER0 1 power down cancellation circuit...

Страница 162: ...ta output P3 6 WR Port data output Port data output P3 7 RD Port data output Port data output XTAL 2 Oscillator operative Oscillator operative XTAL 1 Oscillator operative Oscillator operative VSS 0 V...

Страница 163: ...N PORT 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 W PCON 1 0 PCON bit 1 1 0 SOFT POWER DOWN MODE S6 PORT DATA PORT DATA PD SET CYCLE 1 0 1 0 IOCON bit 0 PORT DATA PORT DATA ALF 0 S1 PORT DATA PORT DATA PORT D...

Страница 164: ...ROM mode S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 W PCON 1 0 PCON bit 1 1 0 SOFT POWER DOWN MODE S6 PORT DATA PORT DATA FLOATING PD SET CYCLE P...

Страница 165: ...Floating Floating Floating External data input External data input External data input External data input External data input External data input External data input External data input Floating Floa...

Страница 166: ...chart internal ROM mode S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 W PCON 1 0 PCON bit 1 1 0 SOFT POWER DOWN MODE S6 PORT DATA PORT DATA PD SET CYCLE...

Страница 167: ...rt external ROM mode S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 W PCON 1 0 PCON bit 1 1 0 SOFT POWER DOWN MODE S6 PORT DATA PORT DATA PD SET CYCLE 1 0...

Страница 168: ...tatus or set to port output floating status The ports are set to data output status by setting bit 0 ALF of the I O control register IOCON 0F8H to 0 when hard power down mode is activated and to float...

Страница 169: ...2 Figure 4 64 Hard power down mode equivalent circuit XTAL 2 XTAL 1 CPU CLOCK Bit Set SMOD HPD RPD GF1 GF0 PD IDL 7 6 5 4 3 2 1 0 CONTROL PCON 87H IOCON 0F8H I O FLOATING Bit Set T32 SERR IZC P3HZ P2H...

Страница 170: ...l input P3 6 WR Port data output Port data output P3 7 RD Port data output Port data output XTAL 2 Oscillator operative Oscillator operative XTAL 1 Oscillator operative Oscillator operative VSS 0 V 0...

Страница 171: ...ernal ROM mode S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 HPDI P3 5 1 0 PCON bit 6 1 0 HARD POWER DOWN MODE S6 PORT DATA PORT DATA HPD SET CYCLE 1 0 1...

Страница 172: ...mode S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 HPDI P3 5 1 0 PCON bit 6 1 0 HARD POWER DOWN MODE S6 PORT DATA PORT DATA HPD SET CYCLE 1 0 1 0 IOCON...

Страница 173: ...ating Floating Floating Floating External data input External data input External data input External data input External data input External data input 0 level input 0 level input Floating Floating F...

Страница 174: ...hart internal ROM mode S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 PCON bit 6 1 0 HARD POWER DOWN MODE S6 PORT DATA PORT DATA HPD SET CYCLE 1 0 1 0 IOC...

Страница 175: ...external ROM mode S1 S2 S3 S4 S5 S6 M1 or M2 M1 XTAL1 1 0 ALE 1 0 PSEN PORT 0 PORT 1 PORT 2 PORT 3 PCON bit 6 1 0 HARD POWER DOWN MODE S6 HPD SET CYCLE 1 0 1 0 IOCON bit 0 ALF 1 S1 HPDI P3 5 1 0 1 0 1...

Страница 176: ...odes By generating the respective interrupt source signals the program can be executed from the interrupt address and can also be continued from the next address after the stop address This method can...

Страница 177: ...M1 M2 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 PCON bit 0 1 0 RESET 1 0 EXECUTE CYCLE RESET CYCLE M1 M2 CPU R...

Страница 178: ...S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE S6 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 PCON bit 0 1 0 RESET 1 0 EXECUTE CYCLE RESET CYCLE CPU RESET CONTROL...

Страница 179: ...1 M2 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 PCON bit 1 1 0 RESET 1 0 EXECUTE CYCLE RESET CYCLE M1 M2 CPU RES...

Страница 180: ...S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 PCON bit 1 1 0 RESET 1 0 EXECUTE CYCLE RESET CYCLE M1 M2 CPU RESET CONTROL...

Страница 181: ...6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 IOCON bit 0 1 0 RESET 1 0 EXECUTE CYCLE RESET CYCLE M1 M2 CPU RESET CONTROL 1 0 PORT...

Страница 182: ...S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 IOCON bit 0 1 0 RESET 1 0 EXECUTE CYCLE RESET CYCLE M1 M2 CPU RESET CONTROL 1 0 PORT DATA 1 PORT DA...

Страница 183: ...ster IE 0A8H prior to setting CPU power down mode and 0 is set in bit 5 RPD of the power control register PCON 87H All six interrupts can be used to cancel idle mode The interrupt conditions are satis...

Страница 184: ...Figure 4 75 Equivalent circuit for DLE and PD mode rancellation by interrupt signal IE0 TCON 1 IE 0 TF0 TCON 5 IE 1 IE1 TCON 3 IE 2 TF1 TCON 7 IE 3 RI TI SCON 0 1 IE 4 EXF2 TF2 T2CON 6 7 IE 5 IE 7 IDL...

Страница 185: ...M mode S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 XTAL1 1 0 ALE S6 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 PCON bit 0 1 0 INT0 or INT1 1 0 INTERR...

Страница 186: ...4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 XTAL1 1 0 ALE S6 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 PCON bit 0 1 0 INT0 or INT1 1 0 INTERRUPT EXECUTE CYCLE...

Страница 187: ...e S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 1 0 1 0 EXECUTE CYCLE WASTE CYCLE 1 0 PORT DATA P...

Страница 188: ...S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M2 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 1 0 1 0 EXECUTE CYCLE WASTE CYCLE 1 0 PORT DATA PORT DATA SOFT POWER DOW...

Страница 189: ...lags in TCON T2CON or SCON clock signals are passed to the CPU control stage and execution is resumed from the next address after the stop address Soft power down mode PD can be cancelled by four diff...

Страница 190: ...S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 XTAL1 1 0 ALE S6 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 PCON bit 0 1 0 INT0 or INT1 1 0 INTERRUPT EXECUTE CYCLE W...

Страница 191: ...S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M2 XTAL1 1 0 ALE S6 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 PCON bit 0 1 0 INT0 or INT1 1 0 INTERRUPT EXECUTE CYCLE WASTE CYCLE I...

Страница 192: ...S2 S3 S4 S5 S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 1 0 1 0 EXECUTE CYCLE WASTE CYCLE 1 0 PORT DATA PORT DATA PORT DATA SOFT POWER DOWN MODE...

Страница 193: ...S6 M1 S1 S2 S3 S4 S5 S6 M1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0 1 0 PORT 1 1 0 PORT 2 1 0 PORT 3 1 0 1 0 1 0 EXECUTE CYCLE WASTE CYCLE 1 0 PORT DATA PORT DATA SOFT POWER DOWN MODE M1 PCON bit 1 INT0 or...

Страница 194: ...to 0 level which separates the external RAM and the peripheral circuit electrically to retain data in the external RAM At the same time a hard power down signal is output the T1 pin of the CPU goes fr...

Страница 195: ...T1 P3 5 10PF 1000 F 0 1 F 74HC08 74HC02 MSM80C154S 83C154S P0 0 P0 1 P0 2 P0 3 P0 4 P0 5 P0 6 P0 7 ALE P2 0 P2 1 P2 2 P2 6 P2 7 P2 3 P2 4 P2 5 I O control signal 5 1K 200K 10 F 74HC02 5 1K 1K 5 1K 74H...

Страница 196: ...CS0 P2 0 P2 1 P2 2 P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 ALE OE WR VCA D7 D6 D5 D4 D3 D2 D1 D0 L Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GND V CC SN74LS373 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9A10 W...

Страница 197: ...MSM80C154S 83C154S 85C154HVS 190 5 INPUT OUTPUT PORTS...

Страница 198: ...INPUT OUTPUT PORTS 191...

Страница 199: ...circuit is indicated in Figure 5 2 When operated as an output port port 0 becomes an open drain output port and when operated as an input port 1 should be set in the port 0 latch to put the port 0 pin...

Страница 200: ...L BUS N PORT 0 WPO Figure 5 2 Port 0 input Output port equivalent circuit in internal ROM mode PC0 7 RA0 7 ACC0 7 READ INTERNAL BUS N P VCC PORT 0 Figure 5 3 Port 0 equivalent circuit during address a...

Страница 201: ...194 PORT0 Accumulator bit Address 1 P0 0 ACC 0 PC RA 0 2 P0 1 ACC 1 PC RA 1 3 P0 2 ACC 2 PC RA 2 4 P0 3 ACC 3 PC RA 3 5 P0 4 ACC 4 PC RA 4 6 P0 5 ACC 5 PC RA 5 7 P0 6 ACC 6 PC RA 6 8 P0 7 ACC 7 PC RA...

Страница 202: ...e VCC supply in parallel The quasi bidirectional port input equivalent circuit is outlined in Figure 5 7 To change port 1 from a quasi bidirectional input port to a high impedance input port 1 is set...

Страница 203: ...MSM80C154S 83C154S 85C154HVS 196 Q D READ INTERNAL BUS WP1 MODIFY Q D C CONTROL P1 VCC P2 P3 PORT 1 N Figure 5 4 Port 1 internal equivalent circuit...

Страница 204: ...S IOH A When accelerator circuit is activated READ N OFF P3 ON R 100k P2 ON R 10k P1 OFF R 500 VCC INTERNAL BUS IOH B When 1 data is held OFF READ N ON P3 R 100k P2 R 10k P1 R 500 VCC INTERNAL BUS IOL...

Страница 205: ...Figure 5 6 Quasi bidirectional port accelerator circuit operation time chart S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 M1 S1 XTAL1 1 0 ALE 1 0 W PORT 1 0 PORT OUT 1 0 P1 2 3TR ON 1 0 CPU BUS 1 0 S2 S6 PSEN...

Страница 206: ...rcuit P3 ON R 100k READ N OFF P2 ON R 10k VCC INTERNAL BUS B 1 data input equivalent circuit P3 ON R 100k IIH OFF ON 10k VCC READ N OFF P2 OFF R 10k VCC INTERNAL BUS C 0 data input equivalent circuit...

Страница 207: ...COUNTER 2 EXTERNAL CLOCK P1 1 T2EX TIMER COUNTER 2 EXTERNAL CONTROL Table 5 2 Port 1 CPU control pin table Table 5 3 Port 1 pin table PORT1 Accumulator bit 1 P1 0 ACC 0 2 P1 1 ACC 1 3 P1 2 ACC 2 4 P1...

Страница 208: ...ata is 1 the 1 data accelerator circuit is activated during output of the data resulting in a higher driving capacity To change port 2 from a quasi bidirectional input port to a high impedance input p...

Страница 209: ...Port 2 address output equivalent circuit for external memory Table 5 4 Port 2 pin table PORT2 Accumulator bit Address 1 P2 0 ACC 0 PC RA 8 2 P2 1 ACC 1 PC RA 9 3 P2 2 ACC 2 PC RA 10 4 P2 3 ACC 3 PC RA...

Страница 210: ...a quasi bidirectional input port to a high impedance input port 1 is set in bit 3 P3HZ of the I O control register IOCON 0F8H The output driver circuit is thus disconnected from the port pin floating...

Страница 211: ...0 P3 3 INT1 EXTERNAL INTERRUPT 1 P3 4 T0 TIMER COUNTER 0 CLOCK P3 5 T1 TIMER COUNTER 1 CLOCK P3 6 WR EXTERNAL DATA MEMORY WRITE STROBE P3 7 RD EXTERNAL DATA MEMORY READ STROBE HPDI HARD POWER DOWN IN...

Страница 212: ...mode 1 is set in bit 0 ALF of the I O control register IOCON 0F8H before PD or HPD mode is activated see Figure 5 11 The port output driver is disconnected from the port pins when power down mode is...

Страница 213: ...C154HVS 206 Bit Set T32 SERR IZC P3HZ P2HZ P1HZ ALF 7 6 5 4 3 2 1 0 IOCON 0F8H Q D READ INTERNAL BUS W PORT MODIFY P2 10k VCC P3 100k I O N PORT1 2 3 POWER DOWN Flag Figure 5 11 Control circuit for po...

Страница 214: ...pull up resistances to the quasi bidirectional input ports Innormaloperations the10kWpull upresistanceisdisconnectedfromtheVCC powersupply when the level of the signal applied to the quasi bidirection...

Страница 215: ...tion circuit When the pin level is dropped to 0 the CPU disconnects the 10 kW pull up resistance from the power supply leaving only the 100 kW pull up resistance connected Since the base current IB of...

Страница 216: ...INPUT OUTPUT PORTS 209 VCC 10k IB VCC P 100k OUT CPU 1 OUT Figure 5 13 Drive circuit for NPN transistor by level shifter IB VCC OUT CPU 0 OUT Figure 5 14 PNP transistor direct connection drive circuit...

Страница 217: ...S6 M1 S1 XTAL1 1 0 ALE 1 0 W PORT 1 0 PORT OUT 1 0 PORT NEW DATA M1 PORT OLD DATA 1M CYCLE OP INC data address DEC data address MOV data address A ORL data address A ANL data address A XRL data addres...

Страница 218: ...CLE OP MOV data address data ORL data address data ANL data address data XRL data address data JBC bit address code address POP data address MOV data address Rr MOV data address Rr MOV data address 1...

Страница 219: ...used according to the instruction to be used and the other where port latch data uneffected by the external signals is used Instructions which use port latch data are listed below INC data address DE...

Страница 220: ...INPUT OUTPUT PORTS 213...

Страница 221: ...MSM80C154 83C154 85C154 214 6 ELECTRICAL CHARACTERISTICS...

Страница 222: ...ELECTRICAL CHARACTERISTICS 215...

Страница 223: ...VCC Ta See below Conditions 2 0 6 2 6 40 85 2 Rating V V C Unit voltage Oscillation fOSC See below 1 24 1 MHz frequency External clock fEXTCLK See below 0 24 MHz operating frequency fOSC 0 Hz Oscilla...

Страница 224: ...put Leakage Current PORT 0 loating EA RESET Pull down Resistor Pin Capacitance Power Down Current Symbol VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL IOH ITL ILI RRST CIO IPD Conditions Except XTAL1 EA and RESE...

Страница 225: ...0 0 25 0 Maximum Power Supply Current Normal Operation ICC mA VCC Freq 24MHz 4 5V 25 0 5V 29 0 6V 35 0 VCC Freq 1MHz 3MHz 12MHz 16MHz 4V 0 8 1 2 3 1 3 8 5V 1 2 1 7 4 4 5 5 6V 1 6 2 3 5 9 7 3 Maximum P...

Страница 226: ...25 VCC 0 1 Parameter Symbol Condition Min Typ Max Unit Input Low Voltage VIL 0 5 V VCC 0 5 Input High Voltage VIH Except XTAL1 EA 0 25 VCC 0 9 V and RESET VCC 0 5 Input High Voltage VIH1 XTAL1 RESET...

Страница 227: ...2 VIH VIL 1 2 3 4 VCC VSS INPUT OUTPUT Note 3 V A Note 2 VIH VIL VCC VSS INPUT OUTPUT V Note 1 VCC VSS INPUT OUTPUT Note 3 VIH VIL A A Note 1 Repeated for specified input pins 2 Repeated for specifie...

Страница 228: ...g Edge 4tCLCL 100 ns tLLPL Instruction Data Read Time from ALE Falling Edge 1tCLCL 30 ns tLLPL From ALE Falling Edge to PSEN Falling Edge 3tCLCL 35 ns tPLPH PSEN Signal Width 3tCLCL 45 ns tPLIV Instru...

Страница 229: ...MSM80C154 83C154 85C154 222 External program memory read cycle tLHLL tAVLL tLLPL tPLPH tLLIV tPLIV tLLAX tAZPL tPXIX tPXIZ tPXAV tAVIV A0 A7 INSTR IN A0 A7 PORT 0 A8 A15 A0 A7 PORT 2 A8 A15 ALE PSEN...

Страница 230: ...ng Edge 0 ns tRHDX RAM Data Read Hold Time from RD Signal Rising Edge 2tCLCL 70 ns tRHDZ Data Bus Floating Time from RD Signal Rising Edge 8tCLCL 100 ns tLLDV RAM Data Read Time from ALE Signal Fallin...

Страница 231: ...DPL DATA IN PORT 0 P2 0 P2 7 DATA or A8 A15 PCH A8 A15 PCH PORT 2 ALE PSEN A8 A15 PCH PCH A0 A7 PCL INSTR IN A0 A7 PCL tLLAX tAVWL tAZRL tRLDV RD tWHLH tLHLL tLLWL tWLWH tAVLL tWHQX A0 A7 RrorDPL DATA...

Страница 232: ...to 85 C Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data V...

Страница 233: ...MSM80C154 83C154 85C154 226 VALID ALE SHIFT CLOCK INPUT DATA MACHINE CYCLE OUTPUT DATA tXLXL tQVXH tXHQX tXHDV tXHDX VALID VALID VALID VALID VALID VALID VALID...

Страница 234: ...measurements are made atVIH logic 1 and VIL 10gic 0 2 Floating VIH VIL VIH VIL VOH VOL VOH VOL Floating The port 0 floating interval is measured from the time the port 0 pin Voltage drops below VIH a...

Страница 235: ...meter Oscillator Freq High Time Low Time Rise Time Fall Time Symbol 1 tCLCL tCHCX tCLCX tCLCH tCHCL Min 0 15 15 Max 24 5 5 Unit MHz ns ns ns ns tCHCX tCHCL tCHCX tCLCH tCLCL 0 7VCC 0 2VCC 0 1 VCC 0 5...

Страница 236: ...7 DESCRIPTION OF INSTRUCTIONS...

Страница 237: ...MSM80C154S 83C154S 85C154HVS 230...

Страница 238: ...is a total of 112 instructions classified into the following groups 1 Arithmetic and logic instructions 15 2 Accumulator operation instructions 7 3 Increment decrement instructions 9 4 Logical operat...

Страница 239: ...iplication Division X Representation of the contents of X X Representation of the contents addressed by contents of X Symbol denoting immediate data Symbol denoting indirect address Equal sign Not equ...

Страница 240: ...R2 data MOV R3 data MOV R4 data MOV R5 data MOV R6 data MOV R7 data SJMP rel AJMP address 11 Page 4 ANL C bit MOVC A A PC DIV AB MOV direct 1 direct 2 MOV direct R0 MOV direct R1 MOV direct R0 MOV dir...

Страница 241: ...C OV C A A C direct address AC OV C A A C Rr r 0 or 1 AC OV C A A C data AB A B A quotient B remainder A B When the contents of accumulator bit 0 thru 3 exceed 9 and when the auxiliary carry AC is 1 6...

Страница 242: ...mulator operation instructions CLR CPL RL RLC RR RRC SWAP A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A 0 A A A4 7 A0 3 272 275 349 350 351 352 361 1 1 1 0 0 1 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 0 1 1 0 0 1...

Страница 243: ...r 0 or 1 A A AND Rr r 0 7 A A AND direct address A A AND Rr r 0 or 1 A A AND data direct address direct address AND A direct address direct address AND data A A OR Rr r 0 7 A A OR direct address A A O...

Страница 244: ...ress A A XOR Rr r 0 or 1 A A XOR data direct address direct address XOR A direct address direct address XOR data A data Rr data r 0 7 direct address data 337 344 343 368 369 367 366 371 370 314 320 32...

Страница 245: ...C OR bit address C C OR bit address C bit address bit address C bit address 1 311 319 273 353 276 260 261 341 342 318 323 354 0 1 1 1 0 1 1 r I7 I6 I5 I4 I3 I2 I1 I0 1 0 0 1 0 0 0 0 I15 I14 I13 I12 I...

Страница 246: ...rect address r 0 7 direct address A direct address Rr r 0 7 direct address 1 direct address 2 direct address Rr r 0 or 1 Rr A r 0 or 1 Rr direct address r 0 or 1 A A DPTR PC PC 1 A A PC 277 316 317 31...

Страница 247: ...3 Rr0 3 r 0 or 1 SP SP 1 SP direct address direct address SP SP SP 1 PC PC 2 SP SP 1 SP PC0 7 SP SP 1 SP PC8 15 PC0 10 A0 10 PC PC 3 SP SP 1 SP PC0 7 SP SP 1 SP PC8 15 PC0 15 A0 15 PC8 15 SP SP SP 1...

Страница 248: ...15 SP SP SP 1 PC0 7 SP SP SP 1 INTERRUPT ENABLE PC PC 2 PC0 10 A0 10 PC0 15 A0 15 PC PC 2 PC PC relative offset PC A DPTR PC PC 3 IF A direct address THEN PC PC relative offset IF A direct address THE...

Страница 249: ...tions CJNE CJNE A data rel Rr data rel 3 3 2 2 PC PC 3 IF A data THEN PC PC relative offset IF A data THEN C 1 ELSE C 0 PC PC 3 IF Rr data r 0 7 THEN PC PC relative offset IF A data r 0 7 THEN C 1 ELS...

Страница 250: ...offset IF Rr data r 0 or 1 THEN C 1 ELSE C 0 PC PC 2 Rr Rr 1 r 0 7 IF Rr 0 r 0 7 THEN PC PC relative offset PC PC 3 direct address direct address 1 IF direct address 0 THEN PC PC relative offset PC P...

Страница 251: ...1 R0 JNC rel 2 2 PC PC 2 IF C 0 THEN PC PC relative offset 0 1 0 1 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 JB bit rel 3 2 PC PC 3 IF bit address 1 THEN PC PC relative offset 0 0 1 0 0 0 0 0 R7 R6 R5 R4 R3 R2...

Страница 252: ...tion External memory instructions Other instruction MOVX A Rr A Rr A DPTR Rr A DPTR A PC PC 1 1 1 1 0 0 0 1 r MOVX A DPTR 1 1 1 0 0 0 0 0 MOVX Rr A 1 1 1 1 0 0 1 r MOVX DPTR A 1 1 1 1 0 0 0 0 NOP 1 1...

Страница 253: ...escription Byte 1 A7 A6 A5 A4 A3 A2 A1 A0 7 0 Byte 2 PC PC 2 SP SP 1 SP PC0 7 SP SP 1 SP PC8 15 PC0 10 A0 10 C AC F0 RS1 RS0 OV F1 P This instruction stores the program counter value return address in...

Страница 254: ...DD A 07H Instruction code Byte 1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 2 A A data C AC F0 RS1 RS0 OV F1 P An 8 bit immediate data value is added to the accumulator The result is placed in the accumulator a...

Страница 255: ...AC F0 RS1 RS0 OV F1 P The data memory location contents addressed by the register r contents are added to the accumulator The result is placed in the accumulator and the flags are updated 0 0 1 0 0 1...

Страница 256: ...6 Instruction code Byte 1 A A Rr r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The register r contents are added to the accumulator The result is placed in the accumulator and the flags are updated 0 0 1 0 1 1 1...

Страница 257: ...7 a6 a5 a4 a3 a2 a1 a0 7 0 Byte 2 A A data address C AC F0 RS1 RS0 OV F1 P The specified data address contents are added to the accumulator The result is placed in the accumulator and the flags are up...

Страница 258: ...on code Byte 1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 2 A A C data C AC F0 RS1 RS0 OV F1 P The carry flag is added to the accumulator and an 8 bit immediate data is added to that result The result is placed...

Страница 259: ...he carry flag is added to the accumulator and the contents of data memory location addressed by the register r contents are added to the accumulator The result is placed in the accumulator and the fla...

Страница 260: ...e 1 A A C Rr r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The carry flag is added to the accumulator and the register r contents are added to the result The result is placed in the accumulator and the flags are...

Страница 261: ...a2 a1 a0 7 0 Byte 2 A A C data address C AC F0 RS1 RS0 OV F1 P The carry flag is added to the accumulator and the specified data address contents are added to that result The result is placed in the a...

Страница 262: ...Description Byte 1 A7 A6 A5 A4 A3 A2 A1 A0 7 0 Byte 2 PC PC 2 PC0 10 A0 10 C AC F0 RS1 RS0 OV F1 P After an increment the program counter PC0 10 is replaced by 11 bit page address data A0 10 The desti...

Страница 263: ...Instruction code Byte 1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 2 A A AND data C AC F0 RS1 RS0 OV F1 P The logical AND between an 8 bit immediate data value and the accumulator contents is determined The re...

Страница 264: ...1 RS0 OV F1 P The logical AND between the accumulator contents and the data memory location contents addressed by the register r contents is determined The result is placed in the accumulator and the...

Страница 265: ...ction code Byte 1 A A AND Rr r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The logical AND between the accumulator contents and the register r contents is determined The result is placed in the accumulator and t...

Страница 266: ...a5 a4 a3 a2 a1 a0 7 0 Byte 2 A A AND data address C AC F0 RS1 RS0 OV F1 P The logical AND between the accumulator contents and the specified data address contents is determined The result is placed in...

Страница 267: ...Instruction code Byte 1 b7 b6 b5 b4 b3 b2 b1 b0 7 0 Byte 2 C C AND bit address C AC F0 RS1 RS0 OV F1 P The logical AND between the carry flag and the specified bit address contents is determined The r...

Страница 268: ...3 Instruction code Byte 1 b7 b6 b5 b4 b3 b2 b1 b0 7 0 Byte 2 C C AND bit address C AC F0 RS1 RS0 OV F1 P The logical AND between the carry flag and the complement of specified bit address contents is...

Страница 269: ...1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 3 data address data address AND data C AC F0 RS1 RS0 OV F1 P The logical AND between an 8 bit immediate data value and the specified data address contents is determ...

Страница 270: ...1 data address data address AND A C AC F0 RS1 RS0 OV F1 P The logical AND between the accumulator and the specified data address contents is determined The result is placed in the specified data addr...

Страница 271: ...tive offset IF Rr data r 0 or 1 THEN C 1 ELSE C 0 C AC F0 RS1 RS0 OV F1 P The data memory location contents addressed by the register r contents are compared with an immediate data value Control is sh...

Страница 272: ...1 0 1 7 0 After execution 35H 0 0 1 0 1 0 1 1 7 0 35H 0 0 1 0 1 0 1 1 7 0 1 Carry flag 0 Carry flag Program counter 15 8 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 7 0 Program counter 15 8 0 0 0 0 0 0 0 0 1 0 1...

Страница 273: ...data THEN PC PC relative offset IF A data THEN C 1 ELSE C 0 C AC F0 RS1 RS0 OV F1 P The accumulator contents are compared with an immediate data value and control is shifted to a relative jump addres...

Страница 274: ...xecution Accumulator 0 1 0 1 0 0 0 0 7 0 After execution 1 Carry flag 0 Carry flag Program counter 15 8 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 7 0 Program counter 15 8 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 7 0 0 0...

Страница 275: ...EN PC PC relative offset IF A data address THEN C 1 ELSE C 0 C AC F0 RS1 RS0 OV F1 P The accumulator contents are compared with the specified data address contents and control is shifted to a relative...

Страница 276: ...fter execution 0 Carry flag 1 Carry flag Program counter 15 8 0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 7 0 Program counter 15 8 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 7 0 0 1 0 1 0 0 0 0 7 0 Byte 2 0 1 0 0 0 1 0 0 7...

Страница 277: ...thru 7 THEN PC PC relative offset IF Rr data r 0 thru 7 THEN C 1 ELSE C 0 C AC F0 RS1 RS0 OV F1 P The register r contents are compared with an immediate data value and control is shifted to a relative...

Страница 278: ...0 Before execution Register 4 0 0 0 0 0 0 0 1 7 0 After execution 1 Carry flag 1 Carry flag Program counter 15 8 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 7 0 Program counter 15 8 0 0 0 0 0 1 0 0 0 1 1 1 0 0 1...

Страница 279: ...on Number of bytes Number of cycles Flags PSW Description Example CLR A Instruction code Byte 1 A 0 C AC F0 RS1 RS0 OV F1 P The accumulator is cleared to 0 and flag is updated 1 1 1 0 0 1 0 0 7 0 Byte...

Страница 280: ...7 0 Instruction code Operation Number of bytes Number of cycles Flags PSW Description Example CLR C Instruction code Byte 1 C 0 C AC F0 RS1 RS0 OV F1 P The carry flag is cleared to 0 1 1 0 0 0 0 1 1...

Страница 281: ...of cycles Flags PSW Description Example CLR P1 5 Instruction code Byte 1 b7 b6 b5 b4 b3 b2 b1 b0 7 0 Byte 2 bit address 0 C AC F0 RS1 RS0 OV F1 P The specified bit address content is cleared to 0 1 0...

Страница 282: ...ration Number of bytes Number of cycles Flags PSW Description Example CPL A Instruction code Byte 1 A A C AC F0 RS1 RS0 OV F1 P Accumulator data 0 is set to 1 and 1 is set to 0 1 1 1 1 0 1 0 0 7 0 Byt...

Страница 283: ...ode Operation Number of bytes Number of cycles Flags PSW Description Example CPL C Instruction code Byte 1 C C C AC F0 RS1 RS0 OV F1 P The carry flag is set to 1 if 0 set to 0 if 1 1 0 1 1 0 0 1 1 7 0...

Страница 284: ...s PSW Description Example CLR B 7 Instruction code Byte 1 b7 b6 b5 b4 b3 b2 b1 b0 7 0 Byte 2 bit address bit address C AC F0 RS1 RS0 OV F1 P The specified bit address content is set to 1 if 0 and set...

Страница 285: ...number is converted to a normal decimal number When the contents of accumulator bits 0 thru 3 100 digit are greater than 9 or when the auxiliary carry AC is 1 6 is added to accumulator bits 0 thru 3...

Страница 286: ...7 0 Before execution Accumulator 0 0 0 1 0 1 0 1 7 0 After execution 0 C 1 C 0 AC 0 AC Accumulator 0 0 1 1 0 0 0 1 7 0 Before execution Accumulator 1 0 0 1 0 1 1 1 7 0 After execution 1 1 1 1 Accumula...

Страница 287: ...scription Example DEC R0 Instruction code Byte 1 Rr Rr 1 r 0 or 1 C AC F0 RS1 RS0 OV F1 P The contents of the data memory location addressed by the register r contents are decremented by 1 0 0 0 1 0 1...

Страница 288: ...r of bytes Number of cycles Flags PSW Description Example DEC A Instruction code Byte 1 A A 1 C AC F0 RS1 RS0 OV F1 P The accumulator contents are decremented by 1 and the flag is updated 0 0 0 1 0 1...

Страница 289: ...n Number of bytes Number of cycles Flags PSW Description Example DEC R7 Instruction code Byte 1 Rr Rr 1 r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The register r contents are decremented by 1 0 0 0 1 1 1 1 1...

Страница 290: ...f cycles Flags PSW Description Example DEC 5AH Instruction code Byte 1 a7 a6 a5 a4 a3 a2 a1 a0 7 0 Byte 2 data address data address 1 C AC F0 RS1 RS0 OV F1 P The specified data address contents are de...

Страница 291: ...ta values are handled as integers without sign The quotient is placed in the accumulator and the remainder in the arithmetic operation register B The carry flag is always cleared and the overflow flag...

Страница 292: ...Flags PSW Description Byte 1 R7 R6 R5 R4 R3 R2 R1 R0 7 0 Byte 2 PC PC 2 Rr Rr 1 r 0 thru 7 IF Rr 0 THEN PC PC relative offset C AC F0 RS1 RS0 OV F1 P The register r contents are decremented by 1 Contr...

Страница 293: ...gister 1 0 0 0 0 1 0 0 0 7 0 Before execution Register 1 0 0 0 0 0 1 1 1 7 0 After execution Program counter 15 8 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 7 0 Program counter 15 8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1...

Страница 294: ...yte 1 R7 R6 R5 R4 R3 R2 R1 R0 7 0 Byte 3 PC PC 3 data address data address 1 IF data address 0 THEN PC PC relative offset C AC F0 RS1 RS0 OV F1 P The specified data address contents are decremented by...

Страница 295: ...1 0 1 1 7 0 Before execution 57H 0 1 1 0 1 0 1 0 7 0 After execution Program counter 15 8 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 7 0 Program counter 15 8 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 7 0 0 1 0 1 0 1 1 1 7...

Страница 296: ...cription Example INC R1 Instruction code Byte 1 Rr Rr 1 r 0 or 1 C AC F0 RS1 RS0 OV F1 P The contents of the data memory location addressed by the register r contents are incremented by 1 0 0 0 0 0 1...

Страница 297: ...r of bytes Number of cycles Flags PSW Description Example INC A Instruction code Byte 1 A A 1 C AC F0 RS1 RS0 OV F1 P The accumulator contents are incremented by 1 and the flag is updated 0 0 0 0 0 1...

Страница 298: ...of cycles Flags PSW Description Example INC DPTR Instruction code Byte 1 DPTR DPTR 1 C AC F0 RS1 RS0 OV F1 P 16 bit contents od the data pointer DPH DPL are incremented by 1 1 0 1 0 0 0 1 1 7 0 Byte...

Страница 299: ...n Number of bytes Number of cycles Flags PSW Description Example INC R5 Instruction code Byte 1 Rr Rr 1 r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The register r contents are incremented by 1 0 0 0 0 1 1 0 1...

Страница 300: ...Flags PSW Description Example INC P1 Instruction code Data address Byte 1 a7 a6 a5 a4 a3 a2 a1 a0 7 0 Byte 2 data address data address 1 C AC F0 RS1 RS0 OV F1 P The specified data address contents are...

Страница 301: ...es Number of cycles Flags PSW Description Byte 1 R7 R6 R5 R4 R3 R2 R1 R0 7 0 Byte 3 PC PC 3 IF bit address 1 THEN PC PC relative offset C AC F0 RS1 RS0 OV F1 P Control is shifted to a relative jump ad...

Страница 302: ...0 0 7 0 Before execution 34 0 1 0 0 1 0 0 0 7 0 After execution Program counter 15 8 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 7 0 Program counter 15 8 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 7 0 0 0 0 1 0 0 1 1 7 0 B...

Страница 303: ...les Flags PSW Description Byte 1 R7 R6 R5 R4 R3 R2 R1 R0 7 0 Byte 3 PC PC 3 IF bit address 1 THEN bit address 0 PC PC relative offset C AC F0 RS1 RS0 OV F1 P Control is shifted to a relative jump addr...

Страница 304: ...0 1 0 7 0 Before execution 46 1 0 1 0 1 0 0 0 7 0 After execution Program counter 15 8 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 7 0 Program counter 15 8 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 7 0 0 1 1 1 0 0 0 1 7 0...

Страница 305: ...rations Number of bytes Number of cycles Flags PSW Description Byte 1 PC PC 2 IF C 1 THEN PC PC relative offset C AC F0 RS1 RS0 OV F1 P Control is shifted to a relative jump address if the carry flag...

Страница 306: ...1 Before execution After execution Program counter 15 8 0 0 0 1 0 1 1 0 1 1 0 1 1 1 1 0 7 0 Program counter 15 8 0 0 0 1 0 1 1 0 1 1 1 1 0 1 0 1 7 0 0 0 0 1 0 1 0 1 7 0 Byte 2 LOC 16DC 16DE 16F5 OBJ...

Страница 307: ...F1 P The accumulator contents are added to the data pointer con tents and the resulting sum is placed in the program counter 1 2 0 1 1 1 0 0 1 1 7 0 Byte 1 Before execution After execution DPH 15 8 0...

Страница 308: ...f bytes Number of cycles Flags PSW Description Byte 1 R7 R6 R5 R4 R3 R2 R1 R0 7 0 Byte 3 PC PC 3 IF bit address 0 THEN PC PC relative offset C AC F0 RS1 RS0 OV F1 P Control is shifted to a relative ju...

Страница 309: ...0 1 1 1 7 0 Before execution 37 0 0 1 1 0 1 1 1 7 0 After execution Program counter 15 8 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 7 0 Program counter 15 8 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 7 0 0 0 1 0 1 0 1 1 7...

Страница 310: ...perations Number of bytes Number of cycles Flags PSW Description Byte 1 PC PC 2 IF C 0 THEN PC PC relative offset C AC F0 RS1 RS0 OV F1 P Control is shifted to a relative jump address if the carry fla...

Страница 311: ...0 7 0 Byte 1 Before execution After execution Program counter 15 8 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 7 0 Program counter 15 8 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 1 7 0 0 0 1 0 0 0 1 0 7 0 Byte 2 LOC 0835 085...

Страница 312: ...ns Number of bytes Number of cycles Flags PSW Description Byte 1 PC PC 2 IF A 0 THEN PC PC relative offset C AC F0 RS1 RS0 OV F1 P Control is shifted to a relative jump address if the accumulator cont...

Страница 313: ...ore execution After execution Program counter 15 8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 7 0 Program counter 15 8 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 0 7 0 0 0 1 1 0 0 0 0 7 0 Byte 2 LOC 00FC 012E OBJ 7030 FB SOU...

Страница 314: ...ns Number of bytes Number of cycles Flags PSW Description Byte 1 PC PC 2 IF A 0 THEN PC PC relative offset C AC F0 RS1 RS0 OV F1 P Control is shifted to a relative jump address if the accumulator cont...

Страница 315: ...fore execution After execution Program counter 15 8 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 7 0 Program counter 15 8 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 7 0 1 1 0 0 1 1 0 1 7 0 Byte 2 LOC 0099 00CA OBJ 04 60CD SO...

Страница 316: ...A12 A11 A10 A9 A8 7 0 Byte 2 PC PC 3 SP SP 1 SP PC0 7 SP SP 1 SP PC8 15 PC0 15 A0 15 C AC F0 RS1 RS0 OV F1 P The contents of the program counter return address are pushed in the stack following an inc...

Страница 317: ...er of bytes Number of cycles Flags PSW Description Byte 1 A15 A14 A13 A12 A11 A10 A9 A8 7 0 Byte 2 PC0 15 A0 15 C AC F0 RS1 RS0 OV F1 P Jump address A0 15 specified by operand are placed in the progra...

Страница 318: ...R1 0AAH Instruction code Byte 1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 2 Rr data r 0 or 1 C AC F0 RS1 RS0 OV F1 P An 8 bit immediate data value is copied to the data memory location addressed by the registe...

Страница 319: ...Instruction code Byte 1 Rr A r 0 or 1 C AC F0 RS1 RS0 OV F1 P The accumulator contents are copied to the data memory location addressed by the register r contents 1 1 1 1 0 1 1 0 7 0 Byte 1 Register 0...

Страница 320: ...5 a4 a3 a2 a1 a0 7 0 Byte 2 Rr data address r 0 or 1 C AC F0 RS1 RS0 OV F1 P The specified data address contents are copied to the data memory location addressed by the register r contents 1 0 1 0 0 1...

Страница 321: ...es Flags PSW Description Example MOV A 05H Instruction code Byte 1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 2 A data C AC F0 RS1 RS0 OV F1 P An 8 bit immediate data is copied to the accumulator and the flag i...

Страница 322: ...code Byte 1 A Rr r 0 or 1 C AC F0 RS1 RS0 OV F1 P The data memory location contents addressed by the register r contents are copied to the accumulator and the flag is updated 1 1 1 0 0 1 1 0 7 0 Byte...

Страница 323: ...SW Description Example MOV A R6 Instruction code Byte 1 A Rr r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The register r contents are copied to the accumulator and the flag is updated 1 1 1 0 1 1 1 0 7 0 Byte 1...

Страница 324: ...OV A P1 Instruction code Byte 1 a7 a6 a5 a4 a3 a2 a1 a0 7 0 Byte 2 A data address C AC F0 RS1 RS0 OV F1 P The specified data address contents are copied to the accumu lator and the flag is updated 1 1...

Страница 325: ...gs PSW Description Example MOV C P3 4 Instruction code Byte 1 b7 b6 b5 b4 b3 b2 b1 b0 7 0 Byte 2 C bit address C AC F0 RS1 RS0 OV F1 P The specified bit address content is copied to the carry flag 1 0...

Страница 326: ...ion code Byte 1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 3 DPTR data DPH I8 15 DPL I0 7 C AC F0 RS1 RS0 OV F1 P A 16 bit immediate data value is copied to the data pointer DPH DPL 3 2 I15 I14 I13 I12 I11 I10...

Страница 327: ...cycles Flags PSW Description Example MOV R5 0AH Instruction code Byte 1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 2 Rr data r 0 thru 7 C AC F0 RS1 RS0 OV F1 P An 8 bit immediate data value is copied to the reg...

Страница 328: ...cles Flags PSW Description Example MOV R1 A Instruction code Byte 1 Rr A r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The accumulator contents are copied to the register r 1 1 1 1 1 0 0 1 7 0 Byte 1 Register 1...

Страница 329: ...n Example MOV R0 5AH Instruction code Byte 1 a7 a6 a5 a4 a3 a2 a1 a0 7 0 Byte 2 Rr data address r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The specified data address contents are copied to the register r 1 0...

Страница 330: ...gs PSW Description Example MOV P1 4 C Instruction code Byte 1 b7 b6 b5 b4 b3 b2 b1 b0 7 0 Byte 2 bit address C C AC F0 RS1 RS0 OV F1 P The carry flag content is copied to the specified bit address 1 0...

Страница 331: ...on Example MOV TCON 50H Instruction code Byte 1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 3 data address data C AC F0 RS1 RS0 OV F1 P An 8 bit immediate data value is copied to the specified data address 0 1 1...

Страница 332: ...a4 a3 a2 a1 a0 7 0 Byte 2 data address Rr r 0 or 1 C AC F0 RS1 RS0 OV F1 P The data memory location contents addressed by the register r contents are copied to the specified data address 1 0 0 0 0 1...

Страница 333: ...ion Example MOV P3 A Instruction code Byte 1 a7 a6 a5 a4 a3 a2 a1 a0 7 0 Byte 2 data address A C AC F0 RS1 RS0 OV F1 P The accumulator contents are copied to the specified data address 1 1 1 1 0 1 0 1...

Страница 334: ...Example MOV 6BH R2 Instruction code Byte 1 a7 a6 a5 a4 a3 a2 a1 a0 7 0 Byte 2 data address Rr r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The register r contents are copied to the specified data address 1 0 0...

Страница 335: ...a4 1 a3 1 a2 1 a1 1 a0 1 7 0 Byte 3 data address 1 data address 2 C AC F0 RS1 RS0 OV F1 P The source data address data address 2 contents are copied to the destination data address data address 1 1 0...

Страница 336: ...umulator con tents and after temporary storage of the sum in the program counter the ROM data contents specified by the program counter are stored in the accumulator The program counter contents are t...

Страница 337: ...he accumulator contents and after temporary storage of the sum in the program counter the ROM data contents specified by the program counter are stored in the accumulator The program counter contents...

Страница 338: ...struction code Byte 1 DPTR A C AC F0 RS1 RS0 OV F1 P The accumulator contents are stored in external data memory RAM addressed by the data pointer contents 1 2 1 1 1 1 0 0 0 0 7 0 Byte 1 Before execut...

Страница 339: ...le MOVX R0 A Instruction code Byte 1 Rr A r 0 or 1 C AC F0 RS1 RS0 OV F1 P The accumulator contents are stored in external data memory addressed by the register r contents 1 2 1 1 1 1 0 0 1 0 7 0 Byte...

Страница 340: ...n code Byte 1 A DPTR C AC F0 RS1 RS0 OV F1 P External data memory RAM contents addressed by the data pointer are stored in the accumulator and the flag is updated 1 2 1 1 1 0 0 0 0 0 7 0 Byte 1 Before...

Страница 341: ...nstruction code Byte 1 A Rr r 0 or 1 C AC F0 RS1 RS0 OV F1 P External data memory RAM contents addressed by the register r contents are stored in the accumulator and the flag is updated 1 2 1 1 1 0 0...

Страница 342: ...ts The operand is always handled as an integer without sign The lower order byte of the result is placed in the accumulator and the higher order byte is placed in the arithmetic operation register B T...

Страница 343: ...0 0 0 0 0 7 0 Instruction code Operation Number of bytes Number of cycles Flags PSW Description Byte 1 PC PC 1 C AC F0 RS1 RS0 OV F1 P The program counter is incremented by 1 without any other change...

Страница 344: ...Instruction code Byte 1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 2 A A OR data C AC F0 RS1 RS0 OV F1 P The logical OR between an 8 bit immediate data value and the accumulator contents is determined The resu...

Страница 345: ...0 RS1 RS0 OV F1 P The logical OR between the accumulator contents and the data memory location contents addressed by the register r contents is determined The result is placed in the accumulator and t...

Страница 346: ...ction code Byte 1 A A OR Rr r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The logical OR between the accumulator contents and the register r contents is determined The result is placed in the accumulator and the...

Страница 347: ...7 a6 a5 a4 a3 a2 a1 a0 7 0 Byte 2 A A OR data address C AC F0 RS1 RS0 OV F1 P The logical OR between the accumulator contents and the specified data address contents is determined The result is placed...

Страница 348: ...Instruction code Byte 1 b7 b6 b5 b4 b3 b2 b1 b0 7 0 Byte 2 C C OR bit address C AC F0 RS1 RS0 OV F1 P The logical OR between the carry flag and the specified bit address content is determined The resu...

Страница 349: ...C 25H 5 Instruction code Byte 1 b7 b6 b5 b4 b3 b2 b1 b0 7 0 Byte 2 C C OR bit address C AC F0 RS1 RS0 OV F1 P The logical OR between the carry flag and the complement of specified bit address content...

Страница 350: ...1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 3 data address data address OR data C AC F0 RS1 RS0 OV F1 P The logical OR between an 8 bit immediate data value and the specified data address contents is determin...

Страница 351: ...e 1 data address data address OR A C AC F0 RS1 RS0 OV F1 P The logical OR between the accumulator and the specified data address contents is determined The result is placed in the specified data addre...

Страница 352: ...ess SP SP SP 1 C AC F0 RS1 RS0 OV F1 P Stack contents addressed by the stack pointer are popped in the specified data address and the stack pointer is decremented by 1 1 1 0 1 0 0 0 0 7 0 Byte 1 Accum...

Страница 353: ...2 SP SP 1 SP data address C AC F0 RS1 RS0 OV F1 P The stack pointer is incremented by 1 and the specified data address contents are pushed in the stack addressed by the stack pointer 1 1 0 0 0 0 0 0...

Страница 354: ...F1 P The stack contents addressed by the stack pointer are popped in the upper order 8 thru 15 of the program counter and the stack pointer is decremented by 1 Then the stack contents addressed by th...

Страница 355: ...ess the priority interrupt And once processing of this interrupt is commenced no other interrupts can be processed until the RETI instruction is executed Stack contents addressed by the stack pointer...

Страница 356: ...s Flags PSW Description Example RL A Instruction code Byte 1 C AC F0 RS1 RS0 OV F1 P All accumulator bits are shifted by one bit to the left The MSB bit 7 is shifted to the LSB bit position bit 0 0 0...

Страница 357: ...e 1 C AC F0 RS1 RS0 OV F1 P The accumulator and the carry flag are connected and all bits are shifted by one bit to the left The carry flag is shifted to the accumulator LSB bit 0 and the accumulator...

Страница 358: ...s Flags PSW Description Example RR A Instruction code Byte 1 C AC F0 RS1 RS0 OV F1 P All accumulator bits are shifted by one bit to the right The LSB bit 0 is shifted to the MSB bit position bit 7 0 0...

Страница 359: ...e 1 C AC F0 RS1 RS0 OV F1 P The accumulator and the carry flag are connected and all bits are shifted by one bit to the right The carry flag is shifted to the accumulator MSB bit 7 and the accumulator...

Страница 360: ...7 0 Instruction code Operation Number of bytes Number of cycles Flags PSW Description Example SETB C Instruction code Byte 1 C 1 C AC F0 RS1 RS0 OV F1 P The carry flag is cleared to 1 1 1 0 1 0 0 1 1...

Страница 361: ...r of cycles Flags PSW Description Example SETB IE 7 Instruction code Byte 1 b7 b6 b5 b4 b3 b2 b1 b0 7 0 Byte 2 bit address 1 C AC F0 RS1 RS0 OV F1 P The specified bit address content is set to 1 1 1 0...

Страница 362: ...RS1 RS0 OV F1 P Relative offset jump data is added subtracted to from the program counter contents following an increment The program counter contents are updated and control is then shifted to the up...

Страница 363: ...le 1 0 0 0 0 0 0 0 7 0 Byte 1 Before execution After execution Program counter 15 8 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 7 0 Program counter 15 8 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 7 0 0 0 0 1 0 0 0 0 7 0 Byt...

Страница 364: ...I0 7 0 Byte 2 A A C data C AC F0 RS1 RS0 OV F1 P The carry flag content and an immediate data value are substracted from the accumulator contents The result is placed in the accumulator and the flags...

Страница 365: ...ata memory location contents addressed by the register r contents are substracted from the accumulator contents The result is placed in the accumulator and the flags are updated 1 0 0 1 0 1 1 0 7 0 By...

Страница 366: ...OV F1 P The carry flag content and the register r contents are substracted from the accumulator contents The result is placed in the accumulator and the flags are updated 1 0 0 1 1 1 1 1 7 0 Byte 1 1...

Страница 367: ...ess C AC F0 RS1 RS0 OV F1 P The carry flag contents and the specified data address contents are substracted from the accumulator contents The result is placed in the accumulator and the flags are upda...

Страница 368: ...PSW Description Example SWAP A Instruction code Byte 1 A4 7 A0 3 C AC F0 RS1 RS0 OV F1 P The contents of the four higher order bits 4 thru 7 of the accumulator are exchanged with the contents of the...

Страница 369: ...code Byte 1 A Rr r 0 or 1 C AC F0 RS1 RS0 OV F1 P The accumulator contents are exchanged with the data memory location contents addressed by the register r and the flag is updated 1 1 0 0 0 1 1 0 7 0...

Страница 370: ...escription Example XCH A R5 Instruction code Byte 1 A Rr r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The accumulator contents are exchanged with the register r contents and the flag is updated 1 1 0 0 1 1 0 1...

Страница 371: ...CH A 7AH Instruction code Byte 1 a7 a6 a5 a4 a3 a2 a1 a0 7 0 Byte 2 A data address C AC F0 RS1 RS0 OV F1 P The accumulator contents are exchanged with the specified data address contents and the flag...

Страница 372: ...C AC F0 RS1 RS0 OV F1 P The lower order bits 0 thru 3 of the accumulator contents are exchanged with contents of the lower order bits 0 thru 3 of the data memory location addressed by the register r...

Страница 373: ...15H Instruction code Byte 1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 2 A A XOR data C AC F0 RS1 RS0 OV F1 P The exclusive OR operation is executed between an immediate data value and the accumulator contents...

Страница 374: ...0 RS1 RS0 OV F1 P The exclusive OR operation is executed between the accumulator contents and the data memory location contents addressed by the register r contents The result is placed in the accumul...

Страница 375: ...nstruction code Byte 1 A A XOR Rr r 0 thru 7 C AC F0 RS1 RS0 OV F1 P The exclusive OR between the accumulator contents and the register r contents is determined The result is stored in the accumulator...

Страница 376: ...1 a7 a6 a5 a4 a3 a2 a1 a0 7 0 Byte 2 A A XOR data address C AC F0 RS1 RS0 OV F1 P The exclusive OR between the accumulator contents and the specified data address contents is determined The result is...

Страница 377: ...1 I7 I6 I5 I4 I3 I2 I1 I0 7 0 Byte 3 data address data address XOR data C AC F0 RS1 RS0 OV F1 P The exclusive OR between an immediate data value and the specified data address contents is determined T...

Страница 378: ...Byte 1 a7 a6 a5 a4 a3 a2 a1 a0 7 0 Byte 2 data address data address XOR A C AC F0 RS1 RS0 OV F1 P The exclusive OR between the accumulator and the specified data address contents is determined The re...

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