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Octek RHINO 5 Скачать руководство пользователя страница 5

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Table of Contents

Preface

Chapter 1: System Overview

1.1 General Specification Overview ......................................2
1.2 Central Processing Unit ...................................................5
1.3 External Cache Subsystem ...............................................5
1.4 DRAM Subsystem ...........................................................5
1.5 PCI Bus ............................................................................6
1.6 Super I/O Subsystem ........................................................6
1.7 Input/Output Subsystem ...................................................7
1.8 BIOS Subsystem ..............................................................7

Chapter 2: Installation and Upgrade

2.1 Setup .................................................................................8
2.2 Installation Precautions ....................................................8
2.3 Operation and Maintenance .............................................8
2.4 CPU Installation ...............................................................9
2.5 CPU Upgrade/ VRM Header .........................................10
2.6 Fast Page mode / EDO DRAM Installation ...................11
2.7 Asynchronous Cache RAM Installation ........................14
2.8 Control of System Speed ................................................14
2.9 Fan voltage .....................................................................15
2.10 Fan Connector ................................................................15
2.11 Reset CMOS ..................................................................15

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Содержание RHINO 5

Страница 1: ...USER S MANUAL RHINO 5 Pentium PCI Local Bus Motherboard...

Страница 2: ...RHINO 5 Pentium PCI Local Bus Motherboard User s Manual Version 1 0 August 1995...

Страница 3: ...tion Ltd Ocean assumes no responsibility in the event that any inaccuracies are found In no event shall Ocean be held liable for any loss or expenses whether directly or indirectly caused by the suppo...

Страница 4: ...rsonal computing to a new level of performance About the Manual The content of this manual is for reference only and is intended to provide basic information for the general user Technical information...

Страница 5: ...Subsystem 6 1 7 Input Output Subsystem 7 1 8 BIOS Subsystem 7 Chapter 2 Installation and Upgrade 2 1 Setup 8 2 2 Installation Precautions 8 2 3 Operation and Maintenance 8 2 4 CPU Installation 9 2 5 C...

Страница 6: ...pendix B Connectors Pinout B 1 Reset Connector P1 24 B 2 Turbo LED Connector P2 24 B 3 Keylock Connector P3 24 B 4 Fan Connector P4 24 B 5 EPMI T B Switch P5 25 B 6 Speaker Connector P6 25 B 7 Header...

Страница 7: ...m Component Map 30 C 2 Layout of RHINO 5 Main Board 31 C 3 Jumper Settings 32 C 3 1 CPU related settings 32 C 3 2 External cache L2 cache setting 35 C 3 3 DRAM 36 C 3 4 Peripheral setup 37 C 3 5 Misce...

Страница 8: ...idth 32 bit PCI expansion bus the I O bottleneck that plagues most PC systems is now removed All of the I O is integrated inside the mainboard to further facilitate system installation The built in ID...

Страница 9: ...chipset Cache Architecture Internal Cache 8KB data cache 8KB code cache External Cache 256KB 512KB 1MB asynchronous 3V Mixed voltage SRAM Memory Subsystem DRAM SIMM sockets 4 x 72 pin 4MB 8MB 16MB 32...

Страница 10: ...Mouse PS 2 Mouse Supports PS 2 Mouse through a 2x4 header Power Management Green functions Support various Power Management schemes BIOS Subsystem BIOS Type AWARD BIOS Shadowing Shadow RAM for System...

Страница 11: ...t functions Fast A20 gate and Fast Reset Clock Enhanced real time clock calendar with battery back up Other Features Power good On board power good signal generation 3 3V supply On board 3 3V supply t...

Страница 12: ...d complying to ANSI IEEE standard 754 1985 1 3 External Cache Subsystem The external cache of RHINO 5 is organized in a direct mapped configuration with sizes of 256KB or 512KB or 1MB It can operate i...

Страница 13: ...ing in add on cards can be configured automatically The PCI local bus implemented in RHINO 5 is fully compliant to v2 0 specification Up to four PCI bus masters are supported Advanced PCI bus buffer m...

Страница 14: ...e same time Therefore up to seven expansion slots can be populated on RHINO 5 Furthermore all the PCI slots can accept PCI bus master cards 1 8 BIOS Subsystem RHINO 5 uses Award ROM BIOS and is stored...

Страница 15: ...ouch a grounded metal object before removing the board from the anti static bag and wear a grounded wrist or ankle strap when handling the components Put the board and peripherals back into the anti s...

Страница 16: ...and dirt are harmful to electronic devices To prevent from accumulating on the motherboard install all mounting plates on the rear of the case Regularly examine your system and if necessary vacuum th...

Страница 17: ...Module and is specially designed to provide a steady power source with voltage of around 2 5V for use by P55C CPU CPU such as P54C P54CT P54CS P54CQS do not need to use the VRM as all the voltage req...

Страница 18: ...starting from right to left consecutively Start to install the SIMM modules IN PAIRS from the right hand side first SM1 SM2 Depending on how your memory is configured you may not need to use all the m...

Страница 19: ...h is at the bottom left corner Insert the bottom edge of the module into the bank at an angle then pull the module in the direction towards yourself so that it is locked into place by the latches loca...

Страница 20: ...256Kx32 10MB 1Mx32 1Mx32 512Kx32 512Kx32 12MB 1Mx32 1Mx32 1Mx32 1Mx32 16MB 2Mx32 2Mx32 256Kx32 256Kx32 18MB 2Mx32 2Mx32 512Kx32 512Kx32 20MB 2Mx32 2Mx32 1Mx32 1Mx32 24MB 2Mx32 2Mx32 2Mx32 2Mx32 32MB 4...

Страница 21: ...equires 8 pieces of 32Kx8 data RAM As they are 28 pin DIP IC they should be stuffed at U2 U6 and U9 U11 as shown below For cache size of 512K bytes or 1M bytes 8 pieces of 64Kx8 or 128Kx8 data SRAM sh...

Страница 22: ...ghly recommended for today s high speed CPUs Extreme high CPU temperature are generated during system operations and may cause abnormal hardware behaviour if system is not cool down 2 11 Reset CMOS If...

Страница 23: ...Memory Address Map Address Size Function 0000000 009FFFF 640 KB System board memory 00A0000 00BFFFF 128 KB Video RAM display buffer 00C0000 00DFFFF 128 KB Reserved for add on cards ROM BIOS 00E0000 00...

Страница 24: ...DMA Page Registers 0A0 0BF Interrupt Controller 2 8259A 0C0 0DF DMA Controller 2 8237A 5 0F0 Clear Math Coprocessor Busy 0F1 Reset Math Coprocessor 0F8 0FF Math Coprocessor 1F0 1F8 Fixed Disk 200 207...

Страница 25: ...round GND B10 A10 I O CHRDY I O SMEMW B11 A11 AEN O O SMEMR B12 A12 SA19 I O I O IOW B13 A13 SA18 I O I O IOR B14 A14 SA17 I O O DACK3 B15 A15 SA16 I O I DRQ3 B16 A16 SA15 I O O DACK1 B17 A17 SA14 I O...

Страница 26: ...O I IRQ11 D4 C4 LA21 I O I IRQ12 D5 C5 LA20 I O I IRQ15 D6 C6 LA19 I O I IRQ14 D7 C7 LA18 I O 0 DACK0 D8 C8 LA17 I O I DRQ0 D9 C9 MEMR I O 0 DACK5 D10 C10 MEMW I O I DRQ5 D11 C11 SD08 I O 0 DACK6 D12...

Страница 27: ...A21 RESERVED GROUND B22 A22 AD 28 AD 27 B23 A23 AD 26 AD 25 B24 A24 GROUND RESERVED B25 A25 AD 24 C BE 3 B26 A26 IDSEL AD 23 B27 A27 RESERVED GROUND B28 A28 AD 22 AD 21 B29 A29 AD 20 AD 19 B30 A30 GR...

Страница 28: ...D B57 A57 5V ACK64 B58 A58 REQ64 5V B59 A59 5V 5V B60 A60 5V PCI Bus Pinout Cont A 5 Direct Memory Access Channels Channe l Function 8 Bit 16 Bit Transfer Block Size 0 Spare 8 bit 64 1 SDLC 8 bit 64 2...

Страница 29: ...d current word count D0 Read Status Register Write Command Register D2 Write Request Register D4 Write Single Mask Register Bit D6 Write Mode Register D8 Clear Byte Pointer Flip Flop DA Read Temporary...

Страница 30: ...rd Output Buffer Full IRQ2 Interrupt from CTLR 2 IRQ8 Real time Clock Interrupt IRQ9 Software Redirected to INT 0AH IRQ2 IRQ10 Reserved IRQ11 Reserved IRQ12 PS 2 Mouse IRQ13 Coprocessor IRQ14 Fixed Di...

Страница 31: ...1 Reset Connector P1 Pin Signal Name 1 Reset 2 Ground B 2 Turbo LED Connector P2 Pin Signal Name 1 Pull_Up_150 2 LED_Turbo B 3 Keylock Connector P3 Pin Signal Name 1 5Vdc 2 Mechanical Key 3 Ground 4 K...

Страница 32: ...3 Ground 4 5Vdc B 7 Header 7 P8 Signal Name Pin Pin Signal Name Ground 1 2 Ground Ground 3 4 Ground 12Vdc 5 6 V IO V IO 7 8 V IO 3 3Vdc 9 10 3 3Vdc 3 3Vdc 11 12 3 3Vdc VCORE 13 14 VCORE VCORE 15 16 VC...

Страница 33: ...3 4 Data 8 Data 6 5 6 Data 9 Data 5 7 8 Data 10 Data 4 9 10 Data 11 Data 3 11 12 Data 12 Data 2 13 14 Data 13 Data 1 15 16 Data 14 Data 0 17 18 Data 15 Ground 19 20 Key DRQx 21 22 Ground I O Write 23...

Страница 34: ...Enable 0 Ground 11 12 Drive Select 1 Ground 13 14 Drive Select 0 Ground 15 16 Motor Enable 1 Ground 17 18 DIR Ground 19 20 STEP Ground 21 22 Write Data Ground 23 24 Write Gate Ground 25 26 Track 00 Gr...

Страница 35: ...6 19 Ground Data bit 5 7 20 Ground Data bit 6 8 21 Ground Data bit 7 9 22 Ground ACK 10 23 Ground BUSY 11 24 Ground PE Paper End 12 25 Ground SLCT 13 26 N C B 13 Serial Port Connector P15 P16 Signal...

Страница 36: ...c 4 12V dc 5 Ground 6 Ground 7 Ground 8 Ground 9 5Vdc 10 5Vdc 11 5Vdc 12 5Vdc B 15 PS 2 Mouse Connector P19 Signal Name Pin Pin Signal Name 5V dc 1 2 N C N C 3 4 N C Data 5 6 N C Ground 7 8 Clock B 16...

Страница 37: ...bo LED P3 Keylock P4 Fan connector P5 EPMI TB Switch P6 Speaker P8 Header 7 P9 External Battery Connector P10 IDE LED Connector P11 Secondary IDE Connector P12 Primary IDE Connector P13 Floppy Drive C...

Страница 38: ...Appendix C Hardware Settings RHINO 5 User s Manual 31 C 2 Layout of RHINO 5 Main Board...

Страница 39: ...ttings are as follows P8 7 9 P8 8 10 P8 11 13 P8 12 14 The four pieces of shunt connectors are to be left in factory setting This configuration works well with all Pentium CPUs P54C P54CQS and P54CS F...

Страница 40: ...C Hardware Settings RHINO 5 User s Manual 33 TOP VIEW OF HEADER 7 BESIDE THE CPU SOCKET 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 4 Top View of Header 7 C...

Страница 41: ...100 Intel P54C 133 Clock multiplier JP2 JP39 P54C P54CQS P54CS B STEP P54CS C STEP P55C 1 2 1 2 reserved reserved x2 5 x2 5 2 3 1 2 reserved reserved reserved reserved 1 2 2 3 x2 x2 x2 x2 2 3 2 3 x1...

Страница 42: ...12V 2 3 C 3 2 External cache L2 cache setting Async Cache Sync Cache selection JP42 Asynchronous Cache 1 2 Synchronous Cache 2 3 Asynchronous L2 cache size JP3 JP4 JP10 256KB 2 3 1 2 2 3 512KB 1 2 1 2...

Страница 43: ...speed voltage tag RAM U8 32Kx8 15ns 5V I 0 data RAM U2 U6 U9 U11 64Kx8 15ns 3 3V I O 1MB cache SRAM location type speed voltage tag RAM U8 32Kx8 15ns 5V I 0 data RAM U2 U6 U9 U11 128Kx8 15ns 3 3V I O...

Страница 44: ...ipheral setup PS 2 MOUSE support JP17 JP18 JP19 Enabled 1 2 2 3 2 3 Disabled 2 3 1 2 1 2 Printer port interrupt JP31 IRQ5 1 2 IRQ7 2 3 DMA request for printer port ECP mode JP32 DRQ1 1 2 DRQ3 2 3 DMA...

Страница 45: ...d drive absent 1 2 2nd drive present 2 3 C 3 5 Miscellaneous Power Good Signal select JP40 External Power Good 1 2 On board Power Good 2 3 CMOS discharge JP21 Clear CMOS 1 2 Preserve CMOS 2 3 Battery...

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