Octek HAWK 486, Руководство пользователя

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GENERAL
FEATURES
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2-9
DUAL BUS DESIGN
It is very important that a high speed system should be
compatible with existing peripherals without lowering the performance.
To be compatible, the I/O slot should run at 8MHz or slower. On the
other hand, the rest of the system are running at full speed.
A dual bus design is employed. A high speed bus links the
CPU, coprocessor, cache memory and main memory. This bus is
synchronous with the clock of the CPU and the data transfer is 32 bits.
Whenever there is a request for transferring to or from I/O slot, the
chipset is responsible for handling the conversion between the buses.
The clock rate of the high speed bus will not be reduced, which
eliminates many compatibility problem.
CPU
High Speed
bus 8Mhz bus
Chip Set I/O Slot
32 Memory bus
Cache
Main
Memory Memory
┌─────┐
│ │
└──┬──┘
│ ┌───────┐ ┌───────┐
├────────────┤ ├──────┤ │