5 DIGIMOD
Card
5.1
Theory of Operation
The DIGIMOD Card contains miscellaneous digital and analog circuitry
for modulation system and CPU card support.
The functions on this board include:
•
Demultiplexing
enable signals for system CD4051s
•
Velocity and ADSR 2 demultiplexing/remultiplexing for the
modulation system
•
Mono controller mixer multiplexing
•
Digital control signals for parameter trimmer addressing and other
miscellaneous system functions.
•
Modulation
system
clocks
Much of the DIGIMOD circuitry explanations refer to the description of
the Modulation and DAC subsystems, and so it would be best to read
those sections prior to proceeding with this section.
5.2
Demultiplexing Enable Signals
The DAC subsystem routes the multiplexed DAC line to 16 CD4051
demultiplexers that are located throughout the VOYETRA. The CPU
must generate control signals to address these demultiplexers so that the
proper analog signal may be refreshed when necessary. Since the
system uses +15V to bias these CD4051s, the control signals, including
address and enable, vary from 0V in logic state LOW to +15V in logic
state HIGH.
When the CPU wants to route the DAC output to a particular
demultiplexing location, it first selects the slot number (0-7) on the
particular CD4051 by setting the low order address bits A0, A1 and A2 to
the number corresponding to the position. These address bits, coming
from the CPU, are +5V logic high, so they cannot be used to drive the
CD4051 directly. Thus, a 7404 level shifter U5 is first used to change the
levels from +5V to +15V high to form A015, A115 and A215. Then, when
the CPU writes to any location in the memory mapped demultiplexers, a
latch pulse is generated by the 74LS26 U4. This latch pulse is used to
latch the 15V address bus by using CD4174 U14 and CD4013 U16. The
outputs, now called Al015, AL115 and AL215 will not change until the
CPU addresses the memory mapped demultiplexers again.
