Table 17–1 BIOS beep codes
Port 80
Code
Beep
Sequence
POST Routine Description
Verify Real Mode
02h
Disable Non-Maskable Interrupt (NMI)
03h
Get CPU type
04h
Initialize system hardware
06h
Disable shadow and execute code from the ROM
07h
Initialize chipset with initial POST values
08h
Set IN POST flag
09h
Initialize CPU registers
0Ah
Enable CPU cache
0Bh
Initialize caches to initial POST values
0Ch
Initialize I/O component
OEh
Initialize the local bus IDE
0Fh
Initialize Power Management
10h
Load alternate registers with initial POST values
11h
Restore CPU control word during warm boot
12h
Initialize PCI Bus Mastering devices
13h
Initialize keyboard controller
14h
BIOS ROM checksum
1-2-2-3
16h
Initialize cache before memory Auto size
17h
8254 timer initialization
18h
8237 DMA controller initialization
1Ah
Reset Programmable Interrupt Controller
1Ch
Test DRAM refresh
1-3-1-1
20h
Test 8742 Keyboard Controller
1-3-1-3
22h
Set ES segment register to 4 GB
24h
Auto size DRAM
1-3-3-1
28h
29h
Initialize POST memory manager
2Ah
Clear 512 KB base RAM
1-3-4-1
2Ch
ROM failure on address line xxxx
1-3-4-3
2Eh
RAM failure on data bits xxxx of low byte of memory bus
2Fh
Enable cache before system BIOS shadow
32h
Test CPU bus-clock frequency
33h
Initialize Phoenix Dispatch Manager
36h
Warm start shutdown
38h
Shadow system BIOS ROM
3Ah
Auto size cache
3Ch
Advanced configuration of chipset registers
3Dh
Load alternate registers with CMOS values
41h
Initialize extended memory for ROMPilot
42h
Initialize interrupt vectors
45h
POST device initialization
2-1-2-3
46h
Check ROM copyright notice
47h
Initialize I20 support
48h
Check video configuration against CMOS
49h
Initialize PCI bus and devices
4Ah
Initialize all video adapters in system
98
Содержание XE-700
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Страница 20: ...Figure 2 3 XE 700 SBC dimensions 20 ...