www.innocomm.com
10
16 KB L1 instruction Cache for M4
•
L1 Data Cache (each core)
32 KB L1 Data Cache (A7)
16 KB L1 Data Cache (M4)
•
The ARM Cortex-A53 Core complex shares
General interrupt controller (GIC)
Global timer
Snoop control unit (SCU)
Unified instruction and data (1MB)
2.2
Memory
WB10-AT i.MX8M SOM is available with up to 3GB of LPDDR4 memory. The default
configuration is 1GB LPDDR4.
2.3
Power Management IC
WB10-AT i.MX8M SOM features Rohm BD7183MWV power management IC.
BD7183MWV is a programmable power management IC that integrates 8 buck
regulators and 7 LDOs to provide all power rails required by SoC and peripherals.
For system management, it provides the following features,
Support software shutdown or hardware power off
External wakeup source
Output monitor
PWROK signal for reset or power off
OVP, UVLO, TSD
2.4
eMMC Storage
The onboard eMMC device is connected on the SD1 pins of the i.MX8M processor in an 8-
bit width configuration.
