T W R - 9 S 1 2 G 1 2 8
J U N E 2 , 2 0 1 0
U S E R G U I D E
6
MEMORY MAP
Figure 1 below shows the target device memory map. Refer to the MC9S12G128 Reference
Manual (RM) for further information.
Figure 1: Memory Map
Address
Module
Size
(Bytes)
0x0000
–0x0009
PIM (port integration module
)
10
0x000A
–0x000B
MMC (memory map control)
2
0x000C
–0x000D
PIM (port integration module)
2
0x000E
–0x000F
Reserved
2
0x0010
–0x0017
MMC (memory map control)
8
0x0018
–0x0019
Reserved
2
0x001A
–0x001B
Device ID register
2
0x001C
–0x001F
PIM (port integration module)
4
0x0020
–0x002F
DBG (debug module)
16
0x0030
–0x0033
Reserved
4
0x0034
–0x003F
CPMU (clock and power management)
12
0x0040
–0x006F
TIM0 (timer module)
48
0x0070
–0x009F
ATD (analog-to-digital converter, 10 bit, 8-channel)
48
0x00A0
–0x00C7
PWM (pulse-width modulator)
40
0x00C8
–0x00CF
SCI0 (serial communications interface)
8
0x00D0
–0x00D7
8
0x00D8
–0x00DF
8
0x00E0
–0x00E7
Reserved
8
0x00E8
–0x00EF
SCI2 (serial communications interface)
8
0x00F0
–0x00F7F SPI1 (serial peripheral interface)
8
0x00F8
–0x00FF
SPI1 (serial peripheral interface)
8
0x0100
–0x0113
FTMRC control registers
20
0x0114
–0x011F
Reserved
12
0x0120
INT (interrupt module)
1
0x0121
–0x013F
Reserved
31
0x0140
–0x017F
CAN
64
0x0180
–0x023F
Reserved
192
0x0240
–0x027F
PIM (port integration module)
64
0x0280
–0x02EF
Reserved
112
0x02F0
–0x02FF
CPMU (clock and power management)
16
0x0300
–0x03BF
Reserved
192
0x03C0
–0x03C7
DAC0 (digital to analog converter)
8
0x03C8
–0x03CF
DAC1 (digital to analog converter)
8
0x03D0
–0x03FF
Reserved
48
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