4
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For adaptation to the digital interface
levels of the connected microcontroller
provides the SJA1124 a VIO
reference voltage pin. Default
SJA1124EVB setting for VIO pin
mapping is J3-3 (VDD).
As alternative J3-4 (P3V3) or J3-4
(P5V0) can be used by populating a
zero-ohm resistor to the appropriate
placeholder. See Figure 4.
Note: Only one placeholder of R33,
R34 and R35 shall be populated with
a zero-ohm resistor. Otherwise
different voltage sources are shorted
and damage on the microcontroller
development boards might occur.
Digital Interface Voltage
Setting
2
STEP-BY-STEP INSTRUCTIONS (cont.)
For the baud rate generators a
reference clock CLK (0.4 … 10 MHz)
must be provided. Default
SJA1124EVB setting for CLK pin
mapping is J2-2 (CLK1_SJA).
As alternative J2-1 (CLK2_SJA) or
J1-5 (CLK3_SJA) can be used by
populating a zero-ohm resistor to the
appropriate placeholder. See Figure 5.
Reference Clock
Setting
3
Figure 4: VIO pin mapping
configuration options
Figure 5: CLK pin mapping configuration
options