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NXP Semiconductors
AH1721
SJA1105SMBEVM UM
AH1721
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
User Manual
Rev. 1.00
— 16 July 2018
6 of 35
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Switch-A and Switch-B can exchange ethernet data via a SGMII connection at
1GBps.
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Port0 of the MPC5748G is wired to Switch-A Port0 using MII-Lite at 100MBps.
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The FE-
PHY is directly connected to MPC5748G’s Port1, also with MII-Lite.
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The 1G-PHYs are connected to Switch-
A’s ports 2 and 3. These links support
speed autonegotiation, but not direction autonegotiation. The actual link speed
depends on the result of the autonegotiation process.
4. Hardware Description
4.1 Power
The SJA1105SMBEVM is powered by a single 12 Volt input. It is advised to use an
adapter that can deliver at least 1 Amp for covering startup current peaks and full-load
situations. The nominal current is ~350mA@12V and depends on the number of active
PHYs, and if the port is connected to a peer.
The power supply topology is shown in Fig 3. The switching regulators for 5V0, 3V3 and
2V5 are controlled by the signal VREG_EN, which can be either fixed to “enable” or
controlled by a combination of an output signal from the PHYs and some sign-off signal
from the CPU. The selection is done with a jumper (J6). With this schema, most of the
board can be switched off when entering sleep mode. For more details see chapter 6.4.
4.2 MPC5748G Microcontroller
The microcontroller runs the user’s software, which controls all components on the
board, e.g. switches, PHYs, LEDs, etc. It also has an ethernet connection to the
switches, so it can receive and send ethernet packets. Therefore, the microcontroller can
work as a host controller for protocols like gPTP, where the software works in conjunction
with hardware features implemented in the switches.
which are only partly implemented in the switches, and need SW assistance.
The MPC5748G features:
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2 e200Z4 32bit cores with 160MHz and 8k I-cache + 4k D-cache
Fig 3.
Power supply topology