NXP Semiconductors S32G2 Скачать руководство пользователя страница 10

Spread spectrum 

S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 

10 

 

NXP Semiconductors 

 

 

 

Figure 14.  VCO frequency out of specified range 

5.  Spread spectrum  

Spread Spectrum clocking is a technique used in electronic design to intentionally modulate the ideal 
position of the clock edge such that the resulting signal’s spectrum is “spread” around the ideal 
frequency of the clock. Spread Spectrum clocking is often used to help meet the regulated EMI 
requirements. 

This section provides the user instructions on how to enable Spread Spectrum functionality.

 

For S32G2, Spread Spectrum clock modulation is only available for the Core, Accelerator and DDR 
PLLs. 

PLL operates in frequency modulation mode when the user sets the following bits as shown in the table 
below –  

Table 3. Mode to enable spread spectrum 

PLLCR[PLLPD] 

PLLFD[SDMEN] 

PLLFM[SSCGBYP] 

PLLFM[SPREADCTL] 

0  

5.1 

Frequency modulation programming 

Modulation depth and modulation frequency programming uses step number (PLLFM[STEPNO]) and 
step size (PLLFM[STEPSIZE]) which can be calculated by using the below equations:  

𝑃𝐿𝐿𝐹𝑀[𝑆𝑇𝐸𝑃𝑁𝑂] =  

𝑓

REF

2  × 𝑓

MOD 

× 𝑃𝐿𝐿𝐷𝐼𝑉[𝑅𝐷𝐼𝑉]

 

 

Equation 1 

 

 

Содержание S32G2

Страница 1: ...esizer DFS modules This application note is intended to provide the user values for commonly used PLL DFS configurations This document is accompanied with an attached clock configurator S32G2_Clock_Co...

Страница 2: ...further diving into this document The following table shows the abbreviations used throughout the document Table1 Acronyms and abbreviations Abbreviation Explanation DFS Digital Frequency Synthesizer...

Страница 3: ...Ls can either be the 20 40 MHz FXOSC or 48 MHz FIRC During boot FIRC_CLK is used as the default PLL reference clock After boot the PLL reference must be changed to FXOSC_CLK Ensure that PLLCLKMUX REFC...

Страница 4: ...ter jitter performance 2 MFI Integer part of LDF 3 MFN Numerator of fractional LDF 4 DIV Division value 5 STEPSIZE Step size for modulation depth and frequency in frequency modulation mode 6 STEPNO Nu...

Страница 5: ...igure 2 DFS block diagram The user needs to configure the value for the below parameters to achieve the target frequencies for CORE_DFSn and PERIPH_DFSn 1 PLL_VCO Respective PLL_VCO frequency serves a...

Страница 6: ...ns tab The options tab provides an interface to select the following 1 FXOSC frequency Figure 3 Selecting FXOSC frequency 2 RDIV RDIV is selected individually for each PLL CORE_PLL PERIPH_PLL ACCEL_PL...

Страница 7: ...n example for A53_CORE_CLK In case SSCG is disabled the calculator provides 500 MHz 800 MHz and 1000 MHz frequency options Figure 8 FA53_CORE_CLK with SSCG disabled And when SSCG modulation is enabled...

Страница 8: ...selected parameters 4 3 Spread spectrum tab With the help of this tab user can calculate values for STEPNO and STEPSIZE to program the modulation depth and the modulation frequency The calculator take...

Страница 9: ...me precaution needs to be taken care while updating the FXOSC frequency in Spread Spectrum tab 2 Target frequency As explained above caution needs to be exercised while enabling or disabling the SSCG...

Страница 10: ...regulated EMI requirements This section provides the user instructions on how to enable Spread Spectrum functionality For S32G2 Spread Spectrum clock modulation is only available for the Core Acceler...

Страница 11: ...modulation depth may differ from the intended modulation depth because of rounding operations applied to PLLFM STEPSIZE and PLLFM STEPNO 5 2 Spread Spectrum Considerations User must adhere to the belo...

Страница 12: ...ere to below conditions 1 18432 2 REF 100 PLL_VCO 5 3 Example code This section illustrates how to configure modulation frequency and modulation depth with the help of an example Example Enabling SSCG...

Страница 13: ...LLDV B MFI 49 CORE_PLL PLLFD B MFN 11520 Enable SSCG at 64 KHz CORE_PLL PLLFM B SSCGBYP 0 Spread spectrum modulation is not bypassed CORE_PLL PLLFM B SPREADCTL 0 Center Spread modulation fMOD 64 KHz M...

Страница 14: ...Clock Configuration using S32DS Clocks Tool S32G2 Vehicle Network Processor Clock Configuration Guide Rev 1 11 2021 14 NXP Semiconductors Figure 17 Clocks diagram view...

Страница 15: ...ration Guide Rev 1 11 2021 NXP Semiconductors 15 Figure 18 Clock Register view NOTE Similar clock configuration can also be done using EB tresos 7 References 1 S32G2 Reference Manual 2 S32G2 Data Shee...

Страница 16: ...the effect of these vulnerabilities on customer s applications and products and NXP accepts no liability for any vulnerability that is discovered Customers should implement appropriate design and ope...

Отзывы: