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NXP Semiconductors QorIQ T1040 Скачать руководство пользователя страница 40

Table 2-12. POR configuration through switches

(continued)

SW2[5:6]

cfg_svr[0:1]

IFC_A[16:17]

Reserved

Reserved

SW2[7]

cfg_dram_type

IFC_A21

DRAM type selection

0: DDR4(1.2V)

1: DDR3L(1.35V)

SW2[8]

cfg_rsp_dis

IFC_AVD

Reserved

Reserved

SW3[1]

cfg_eng_use0

IFC_WE0

Sys_clock selection

0: differential sys_clk is
selected

1:single sys_clk is
selected

SW3[2:3]

cfg_eng_use[1:2]

Reserved

Reserved

Reserved

SW3[4]

BOOT_FLASH_SEL

-

Boot flash selection

0: NOR Flash

SW3[5:7]

CFG_VBANK[0:2]

-

Flash bank select

0: Default

SW3[8]

TEST_SEL_N

TEST_SEL_B

-

0: T1020

1: T1040

1. For SW3[4] : BOOT_FLASH_SEL, it can act as boot flash selection. When BOOT_FLASH_SEL=0, NOR Flash is boot

flash, when BOOT_FLASH_SEL=1, NAND Flash is boot flash.

2. SW3[5:7] can be used to change the staring address for the memory banks. For example, the NOR FLASH memory is

divided into eight memory banks with 16MB size each. Eight different U-Boot image can be programmed into each
memory bank, though normally only settings for bank 0 and bank 4 are used. When NOR FLASH is selected as boot flash
(CS0 is connected to NOR FLASH by setting SW3[4] to ON, RCW[0:8] is set to 0_0111_xxxx using SW1[1:8] and SW2[1]),
a different U-Boot image can be selected to boot up the board, by setting SW3[5:7].

For other boot sources configured by the DIP switch, see the QorIQ T1040 Reference Manual (T1040RM).

DIP switch definition

QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015

40

Freescale Semiconductor, Inc.

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Содержание QorIQ T1040

Страница 1: ...QorIQ T1040 Reference Design Board User Guide Document Number T1040RDBPAUG Rev 0 06 2015...

Страница 2: ...QorIQ T1040 Reference Design Board User Guide Rev 0 06 2015 2 Freescale Semiconductor Inc...

Страница 3: ...15 2 4 Reset 18 2 5 DDR 18 2 6 SerDes port 20 2 6 1 PCIe support 21 2 6 2 SGMII support 22 2 6 3 QSGMII support 22 2 6 4 SATA support 23 2 7 Ethernet controllers 23 2 8 Ethernet management interface 2...

Страница 4: ...4 Software version register SWVER 46 3 2 5 Reset control register RSTCON1 46 3 2 6 Reset control register RSTCON2 47 3 2 7 INTSR 48 3 2 8 Flash control and status register FLHCSR 49 3 2 9 Fan control...

Страница 5: ...4 2 Other boot source settings 59 4 4 3 Switch detailed description 59 4 5 SDK Build details 60 4 6 Flashing and updating images 60 4 6 1 Flashing images on and booting from NOR flash 60 4 6 2 Flashi...

Страница 6: ...QorIQ T1040 Reference Design Board User Guide Rev 0 06 2015 6 Freescale Semiconductor Inc...

Страница 7: ...A To request access to these documents contact your local field applications engineer or sales representative Table 1 1 Related documentation Document name Description QorIQ T1040 T1020 Data Sheet T10...

Страница 8: ...st Controller eSPI Enhanced Serial Peripheral Interface FXS Foreign Exchange Station FXO Foreign Exchange Office I2C Inter Integrated Circuit IFC Integrated Flash Controller JTAG Joint Test Action Gro...

Страница 9: ...1 GB NOR 16 bit non multiplexed 128 MB support of eight virtual banks Ethernet Two onboard RGMII 10 100 1G Ethernet ports PHY 0 remains powered up during deep sleep One onboard SGMII 10 100 1G Etherne...

Страница 10: ...ce and the T1040RDB board Peripheral access management unit CoreNet Coherency Manager Security monitor Power management SD eSDHC eMMC 2x DUART 16b IFC eSPI 4x GPIO 32 64 bit DDR3L 4 memory controller...

Страница 11: ...SATA QE TDM DUART RGMII USB2 0 COP DDR3 I2C Mini PCle PClex1 QSGMII QSGMII F104S8A QGMII Copper Magnetic X4 Magnetic X4 RJ45 X4 RJ45 X4 Magnetic GSTS009LF RTL8211DN SGMII Copper 2Pin Conn FXO Relay F...

Страница 12: ...Block diagram QorIQ T1040 Reference Design Board User Guide Rev 0 06 2015 12 Freescale Semiconductor Inc...

Страница 13: ...ace JTAG COP port Connectors headers jumper push buttons and LED Temperature DIP switch definition 2 1 Processor The T1040RDB supports as many features of the T1040 as possible as detailed in the foll...

Страница 14: ...owing goals guide the power supply architecture Monolithic power supply for VCC that powers internal cores and platform logic T1040RDB can access IR36021 via software to check the current and voltage...

Страница 15: ...PLL1 AVDD_SD1_PLL2 AVDD_PLAT AVDD_D1 AVDD_CGA1 AVDD_CGA2 USB_SVDD 1 2 USB_HVDD 1 2 USB_OVDD 1 2 S1VDD 1 7 X1VDD 1 5 T1040 O1VDD 1 3 OVDD 1 8 D1_MVREF VDD_IP TH_VDD FA_VL PROG_MTR PROG_SFP EVDD1 DVDD 1...

Страница 16: ...Ethernet clocks USB clock The architecture of the clock section is shown in the figure below Clocks QorIQ T1040 Reference Design Board User Guide Rev 0 06 2015 16 Freescale Semiconductor Inc...

Страница 17: ...MPEX2_REFCLK_P N 100M T1040 DDRCLK 66 66MHz USB_REFCLK 24MHz SYSCLK 100MHz SD_REFCLK1_P N 125MHz QSG2_REFCLK_P N 125MHz QSG1_REFCLK_P N 125MHz F104S8A F104S8A MPEX1_REFCLK_P N 100M PEX_REFCLK_P N 100...

Страница 18: ...SW_RST 7 CPLD COP_HRST_N 6 5 4 3 2 1 0 EC2_RST_N RGMII GE PHY2 DDR3 DDR3L CORE_power IR36021 VCORE_PGD NOR FLASH PEX SLOT MINI PEX SLOT MINI PEX SLOT SGMII GE PHY QSGMII GE PHY MPEX2_RST PEX_RST MPEX...

Страница 19: ...latforms support all types ranks and speeds of DIMMs within the specification of the T1040 not all combinations of these three exist on the memory market Thus the system is shipped with a representati...

Страница 20: ...x1 5 Gbit s SATA x1 1 5 3 Gbit s The following table explains the SerDes protocols supported on the T1040RDB board Table 2 2 SerDes protocol distribution SerDes SRDS_PRTCL A B C D E F G H Option T1040...

Страница 21: ...SATA SD1_RXn TXn_P N SD1_RXn TXn_P N SD1_RXn TXn_P N SD1_RXn TXn_P N PI3PCIE3212 PI3PCIE3212 PI3PCIE3212 PI3PCIE3212 QSGMII1_RX TX MPEX 2 PEX 2 PEX 3 SATA Mini_PCle SLOT PCle SLOT F104S8A QSGMII_PHY n...

Страница 22: ...ws the connectivity of the SGMII interface T1040 SGMII MDIO MDC RTL8211DN Transformer RJ 45 Port EMI1 SGMII Figure 2 6 SGMII connection 2 6 3 QSGMII support The T1040RDB board supports evaluation of t...

Страница 23: ...ontrollers EC which can connect to the Ethernet PHYs using the MII or RGMII protocols On the T1040RDB board the EC1 and EC2 ports operate in the RGMII mode only Both ports connect to the Realtek RTL82...

Страница 24: ...MDIO MDC Figure 2 8 RGMII connection 2 8 Ethernet management interface The T1040 Ethernet management interface EMI1 is used with the onboard RGMII SGMII and QSGMII PHYs The figure below shows the EMI...

Страница 25: ...urces equally available to both local and remote systems The T1040RDB board uses I2C1 port to access onboard devices such as SPD on the DDR3L DIMM thermal sensor ADT7461 and core power regulator IR360...

Страница 26: ...50 I2C_ADDR 0x08 Test_mode_ADDR 0x0A I2C_ADDR 0x6A DVDD I2C2_MPEX1_SCL I2C2_MPEX1_SDA FET Isolation 3V3 I2C1_SCL_SLP IR36021 Core_Power IDT9FGV0641 I2C1_SDA_SLP Channel 1 Channel 2 Channel 3 Figure 2...

Страница 27: ...to 3 3V SPI_CS3 SPI_CS2 SPI_CS1 Le88266 SLAC Le88266 SLAC TDM Riser card connector N25Q512A 64MB FLASH SPI_CS0 Figure 2 11 SPI bus connections 2 11 Local bus The T1040 Integrated Flash Controller IFC...

Страница 28: ...2 3 IFC bus address CS Memory Address Bus width CS0 NOR flash 0xe8000000 16 bit CS1 NAND flash 0xff800000 8 bit CS2 CPLD 0xffdf0000 8 bit If SW3 4 is OFF Table 2 4 IFC bus address CS Memory Address Bu...

Страница 29: ...to the USB ports with appropriate protection circuitry and power supplies The USB features are as follows High speed 480 Mbit s full speed 12 Mbit s and low speed 1 5 Mbit s operation Host mode Dual s...

Страница 30: ...diff imp USB Type A INSTALLED Host mode default 5V0 18 2K 51 1K 18 2K 51 1K MIC2506YM Figure 2 14 USB connection 2 14 Serial port The T1040 processor has two UART controllers which provide RS 232 sta...

Страница 31: ...100pF RS232_TXD1 A1 J13A RJ45_2X1 100pF 100pF 100pF C277 C278 C279 RS232_RXD1 RS232_RTS1 RS232_CTS1 A2 A3 A4 A5 A6 A7 A8 17 18 19 DVDD U42 3V3 13 12 11 10 9 5 14 15 NC3 GND 7 6 8 4 3 2 1 16 VCCA A1 O...

Страница 32: ...rovides a line interface which meets the requirements of short and medium loop up to 1500 Ohms total at 1 REN applications Features include high voltage switching regulator line test capabilities inte...

Страница 33: ...mputer through the Ethernet port or USB port A setup using a USB based probe is shown in the figure below PC USB Port USB probe T1040RDB COP Port Figure 2 17 Debugger connection The 16 pin generic hea...

Страница 34: ...processor and JTAG COP connector 9 TMS Connected directly between the processor and JTAG COP connector 10 NC Not connected 11 SRESET Routed to the RESET PLD SRESET to the processor is generated from...

Страница 35: ...B platform Table 2 7 Connector on board Reference Designators Used For Notes J1 UDIMM J3 COP JTAG Used for debugging T1040 J5 SD card J13 2 ports UART Table continues on the next page Chapter 2 Archit...

Страница 36: ...eader on Board Reference Designators Used For Notes J26 Altera CPLD Header Used for programming the Altera CPLD device J28 IR36021 Header Used for programming IR36021 2 17 3 Jumper The below table des...

Страница 37: ...e below lists all the LEDs on the T1040RDB board Table 2 11 LEDs on board LED Part identifier Color Used for Controlled by 3 3 V power supply LED D44 Green Power on 3 3 V power rail Status LED D43 Gre...

Страница 38: ...rature failure I2C Bus T1040 TEMP_ANODE Thermal sensor ADT7461 DXP1 DXN TEMP_CATHODE THERM ALERT THERM2 OVER ALARM THERM ALARM CPLD PWM FAN_Power Figure 2 20 Thermal Sensor connection 2 19 DIP switch...

Страница 39: ...Switch Signal name Pin Name Signal meaning Setting SW1 1 8 cfg_rcw_src 0 7 IFC_AD 8 15 Reset Configuration word source Detail description see T1040 RM SW2 1 cfg_rcw_src 8 IFC_CLE Reset Configuration...

Страница 40: ...OOT_FLASH_SEL 0 NOR Flash is boot flash when BOOT_FLASH_SEL 1 NAND Flash is boot flash 2 SW3 5 7 can be used to change the staring address for the memory banks For example the NOR FLASH memory is divi...

Страница 41: ...he CPLD memory map 3 1 CPLD programming To program CPLD 1 Connect Altera USB blaster to the CPLD header 2 Run altera 61 quartus bin quartus exe to open Quartus II 3 Select Tools Programmer from the me...

Страница 42: ...4 Click the Hardware Setup button to find the USB blaster connected to the PC CPLD programming QorIQ T1040 Reference Design Board User Guide Rev 0 06 2015 42 Freescale Semiconductor Inc...

Страница 43: ...Right click EPM240 select Change File from the context menu and find the pof file 7 Select Program Configure Verify Blank Check checkboxes Chapter 3 CPLD specification QorIQ T1040 Reference Design Boa...

Страница 44: ...e section 3 2 6 47 12 INTSR 8 R See section 3 2 7 48 13 Flash control and status register FLHCSR 8 R W See section 3 2 8 49 14 Fan control and status register FANCSR 8 R W 3 2 9 49 15 Panel LED contro...

Страница 45: ...h offset 1h Bit 0 1 2 3 4 5 6 7 Read CHIPID2 Write Reset 1 0 1 0 1 0 1 0 CHIPID2 field descriptions Field Description 0 7 CHIPID2 0xaa Identification of the CPLD image 3 2 3 Hardware version register...

Страница 46: ...Reserved EC1_RST EC2_RST SG_RST QSG1_RST QSG2_RST XG_RST Write w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 RSTCON1 field descriptions Field Description 0 SW_RST 0 No reset occurs 1 Writing logi...

Страница 47: ...base 11h offset 11h Bit 0 1 2 3 4 5 6 7 Read Reserved TDMR_RST PEX_RST MPEX1_ RST MPEX2_ RST Write w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 RSTCON2 field descriptions Field Description 0 3 This field is...

Страница 48: ...D image revision INTSR field descriptions Field Description 0 THERM_INT 0 No interrupt occurs 1 Board over temperature interrupt occurs 1 SG_INT 0 No interrupt occurs 1 SGMII PHY RTL8211DN interrupt o...

Страница 49: ...tch status is 1 3 SW_BANK_SEL1 0 NOR flash bank select bit1 of switch status is 0 1 NOR flash bank select bit1 of switch status is 1 4 SW_BANK_SEL2 0 NOR flash bank select bit2 of switch status is 0 1...

Страница 50: ...n 0 STS_LED 0 Panel STATUS LED off 1 Panel STATUS LED on 1 FXS1_LED 0 Panel FXS1 LED off 1 Panel FXS1 LED on 2 FXS2_LED 0 Panel FXS2 LED off 1 Panel FXS2 LED on 3 FXS3_LED 0 Panel FXS3 LED off 10 Pane...

Страница 51: ...PI_CS3 select TDMR SPI CS1 1 SLEEP_EN Before entering deep sleep mode set 1 to this bit after exiting deep sleep mode set 0 to this bit 0 Normal operation 1 Deep sleep enable bit 2 3 REQ_MD 00 No rese...

Страница 52: ...BOOTCFG1 Address 0h base 19h offset 19h Bit 0 1 2 3 4 5 6 7 Read cfg_rcw_src 0 7 Write Reset BOOTCFG1 field descriptions Field Description 0 7 cfg_rcw_src 0 7 NOTE For more information see QorIQ T104...

Страница 53: ...field is reserved 2 3 cfg_svr 0 1 cfg_svr bit for T1040 Power on reset use 4 This field is reserved 5 7 cfg_eng_use 0 2 cfg_eng_use bit for T1040 Power on reset use Chapter 3 CPLD specification QorIQ...

Страница 54: ...CPLD memory map QorIQ T1040 Reference Design Board User Guide Rev 0 06 2015 54 Freescale Semiconductor Inc...

Страница 55: ...for use default configuration should be CPU 1 4 GHz DDR 1600 MT s The steps are 1 Attach an RS 232 cable between the T1040RDB UART0 port and host computer 2 Open a serial console tool on the host com...

Страница 56: ...nterleaving Mode CS0 CS1 Flash 256 MiB L2 256 KiB enabled Corenet Platform Cache 256 KiB enabled Using SERDES1 Protocol 102 0x66 NAND 1024 MiB MMC FSL_SDHC 0 PCIe1 Root Complex no link regs 0xfe240000...

Страница 57: ...rted in U Boot L2 switch ETH7 Not supported in U Boot 0xfe4e2000 L2 switch ETH8 Not supported in U Boot L2 switch ETH9 Not supported in U Boot L2 switch ETH10 Not supported in U Boot L2 switch 1 Conne...

Страница 58: ...000 0XEBF1FFFF QUICC Engine microcode alt bank 64KB 0XEBF00000 0XEBF0FFFF FMan microcode alternative bank 64KB 0xE9300000 0XEBEFFFFF rootfs current bank 43MB 0XE8800000 0XE88FFFFF Hardware device tree...

Страница 59: ...OFF OFF OFF ON OFF OFF SW3 1111 0001 OFF OFF OFF OFF ON ON ON OFF SPI boot SW settings DIP Switch binary value 1 2 3 4 5 6 7 8 SW1 0010 0010 ON ON OFF ON ON ON OFF ON SW2 1011 1011 OFF ON OFF OFF OFF...

Страница 60: ...W programming on current bank from U Boot prompt For T1040RDB use rcw t1040rdb RR_P_66 rcw_1400MHz bin NOTE This RCW can change depending upon the requirements tftp 1000000 rcw bin protect off all era...

Страница 61: ...00 fsl_fman_ucode bin protect off all Un Protect Flash Bank 1 erase 0xebf00000 ebf1ffff done Erased 1 sectors cp b 3000000 0xebf00000 10000 Copy to Flash 9 8 7 6 5 4 3 2 1 done U Boot binary programmi...

Страница 62: ...NAND boot images The steps for flashing and updating images for NAND are as follows All operations are done on the target in the U Boot console 1 Write PBL1 bin to NAND from offset 0x0 tftp 100000 PB...

Страница 63: ...d from block 0x820 tftp 100000 fsl_fman_ucode_xx bin mmc write 100000 820 block_number 4 Shut down the board 5 Change board switch configuration for SD boot 6 Switch on the board NOTE For more informa...

Страница 64: ...th 64 bit configuration on T1040RDB setenv my_kern tftp 0x1000000 uImage_64bit setenv my_fs tftp 0x2000000 rfs_e5500 bin setenv my_dtb tftp 0x00c00000 t1040rdb dtb setenv my_boot bootm 0x1000000 0x200...

Страница 65: ...tory Table A 1 summarizes revisions to this document Table A 1 Revision history Revision Date Description 0 06 2015 Initial release QorIQ T1040 Reference Design Board User Guide Rev 0 06 2015 Freescal...

Страница 66: ...QorIQ T1040 Reference Design Board User Guide Rev 0 06 2015 66 Freescale Semiconductor Inc...

Страница 67: ...imitation consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance ma...

Страница 68: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information NXP T1040D4RDB PA...

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