NXP Semiconductors QorIQ LS1028A, Справочное руководство, Страница: 23 / 112

Table 6. LS1028ARDB clocks (continued)
Part
identifier Clock generator Clock Specifications Destination
U91
3
27 MHz crystal
DP_REFCLK_P
DP_REFCLK_N
Frequency: 27 MHz Display port
Y3 25 MHz crystal
ETH_XTALIN
ETH_XTALOUT
Frequency: 25 MHz SGMII PHY
1. The enable/disable for 100 MHz clocks to the M.2 connectors (J16 and J18/J20) is controlled by CPLD. The CPLD detects
the CARD presence on the M.2 slots and enables the OUT 6 and 7 of the clock generator accordingly. Since, both the
outputs are controlled from the same OE, 100 MHz clocks to the M.2 slots are enabled even if only one of the M.2 slots is
populated.
2. The Y2 oscillator provides an option for stable 125 MHz CLK_IN to the 1588 block. The option can be enabled by mounting
R388 and removing R387 that is mounted on the board by default.
3. The U91 oscillator provides an option for a low jitter clock input for Display interface. Clock from U91 can be enabled by
removing C646, C647 and mounting C705, C706. The C646 and C647 capacitors are mounted by default.
2.4 DDR interface
The LS1028ARDB board supports four 1G x8 DDR4 SDRAM memory chips supporting data transfer rates of up to 1.6 GT/s and
one 1G x8 DDR4 SDRAM memory chip for supporting ECC.
The address and control/command signals to the DDR4 SDRAM memory chips are routed in as per the Fly-by topology and are
terminated to VTT (0.6 V). The data bus and associated signals, such as DM and DQS/DQS_B have one-to-one byte wise
connections to the individual x8 DDR4 memories. The ECC nibble goes to the fifth DDR4 memory. The part number of the SDRAM
memory chips is MT40A1G8SA-075:E (from Micron Technology).
Following are the characteristics of the LS1028A DDR4 memory controller:
• Up to 1.6 GT/s
• Supports 32-bit operation (with ECC support)
• Supports x8 devices
• Supports two chip selects, D1_MCS0_B and D1_MCS1_B; however, on board only D1_MCS0_B chip select is supported
• IOs powered by 1.2 V power supply from MC34716EP switch regulator
The MC34716EP switch regulator generates the following different power supplies for the DDR4 controller IO, memory devices,
and terminations: VCC_GVDD_S (1.2 V), VTT (0.6 V) and VREFCA (0.6 V). The memory interface including all the necessary
termination and I/O power are routed, as shown in the following figure.
DDR interface
QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018
NXP Semiconductors COMPANY CONFIDENTIAL
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