NXP Semiconductors PXN2020, Справочное руководство, Страница: 1030 / 1376

Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
31-40 Freescale Semiconductor
Data Bit Synchronization (Left Shifted Edges)
This kind of sample counter synchronization happens if the transmitter is faster than the receiver. The reset
behavior of the sample counter is shown in
Figure 31-35 . The sample counter reset condition is:
1. The data bit N – 1 is sampled as 1, and
2. The data bit N is sampled as 0, and
3. A falling edge consisting of three consecutive 1-samples and a following 0-sample is detected, and
4. The 0-sample of the falling edge is received at data bit N sample j, with 11

j

16.
If the condition is fulfilled, the sample counter is reset 16 RCLK cycles after the 0-sample of the falling
edge condition was received. The bit counter is increased by 1.
Figure 31-35. Data Bit Synchronization (Left Shifted Edges)
If the 0-sample of the falling edge condition is received at sample 9 or 10, no sample counter
synchronization is performed.
31.4.5.3.18 Stop Bit Verification
The reception of a valid stop bit is verified if at least two out of the sample RS8, RS9, and RS10 are
sampled high. If this is not that case, a framing error is detected. Noise is detected if not all of the samples
are of the same value. The results of the stop bit verification are summarized in
Table 31-32 .
Table 31-32. Stop Bit Verification
[RS8, RS9, RS10] Stop Bit Verified Framing Error Detected Noise Detected
000 No Yes No
001 No Yes Yes
010 No Yes Yes
100 No Yes Yes
011 Yes No Yes
101 Yes No Yes
110 Yes No Yes
111 Yes No No
VOTING
DATA
RCLK
RXD
2 3
RSC
4 5 6 7 8 9 10 11 12 13 14 15 16 1
wrap
sample counter reset
left shifted falling edge
2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
VOTING
DATA
reset
VOTING
DATA
DATABIT N-1
FALLING
EDGE
2 3 4 5 1
DATABIT N+1 DATABIT N