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NXP Semiconductors
UM11111
PCAL6416AEV test board user manual
UM11111
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
User manual
Rev. 1.0 — 12 April 2018
3 / 16
1 Introduction
This user manual describes how to use NXP's PCAL6416AEV test board. This board is
designed for testing functional characteristics of the PCAL6416AEV part, saving time for
NXP customer qualification of the 16-bit Agile GPIO expander. This board works with
NXP's Fm+ demo board (OM13260) or any customer I
2
C-bus controller. It has a socket
for VFPGA24 3x3 mm, a 14-pin connector for FM+ demo board using 3.3V, and two
external power supply TPs for VDDI and VDDP of the PCAL6416AEV, as well as an I
2
C-
bus header for customer I
2
C controller.
2 Features and benefits
•
Direct connection to OM13320 Fm+ Development kit
•
External I
2
C-bus connection
•
Isolated power rail for power measurement
•
Socket of VFPGA24 3x3 mm with 0.30 mm ball size
•
Flexible power supply configuration: 3.3V or external supply
•
Direct connection to OM13303 GPIO Target board for I/O visualization
•
Jumper configuration of device I
2
C address
•
LED indicators for power and INT
•
Scope ground connection loop
3 Hardware description
1. Socket U1 for VFBGA24 3x3 mm with 0.30 mm ball size packet
2. Connection to Fm+ demo board (OM13260) port A, B, C or D: CN2 is a 2x8 female
connector
3. Slave device address selection: J6 is a 2x2 male header
a. Slave device address = 0x010-0001(42h) when 1-2 is connected
b. Slave device address = 0x010-0000(40h) when 3-4 is connected
4. VDDI power selection: J4 is a 1x3 header. This jumper header is for selection VDDI
(I2C and internal logic power). The power is from Fm+ demo board 3.3V or external
power from TP3
a. VDDI = TP3 (VDDI_IN: external power) when J4 is opened and J5 is connected
b. VDDI = 3.3V from Fm+ demo board when J4: 1-2 is connected and J5 is
connected
c. VDDI = 5V from Fm+ demo board when J8: 1-2 & J4: 2-3 are connected and J5 is
connected
5. VDDP (IO port) power selection: J1 is a 1x3 header. This jumper header is for
selection VDDP (IO port power). The power is from Fm+ demo board 3.3V or external
power form TP2.
a. VDDP = TP2 (VDDP_IN: external power) when J1 is opened and J3 is connected
b. VDDP = 3.3V from Fm+ demo board when J1: 2-3 is connected and J3 is
connected
c. VDDP = 5V from Fm+ demo board when J8: 1-2 & J1: 1-2 is connected and J3 is
connected
6. VDDI external power input by TP3 (VDDI_IN) and TP4 (GND)
7. VDDP external power input by TP2 (VDDP_IN) and TP5 (GND)
8. External I2C SDA signal input from CN1 (SDA: Beagle master)