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PCA9665_2
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
74 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
Fig 38. Bus timing (read cycle)
Fig 39. Parallel bus timing (write cycle)
A0 to A1
CE
RD
D0 to D7
(read)
002aac693
t
su(A)
t
h(A)
t
su(CE_N)
t
h(CE_N)
t
w(RDL)
t
w(RDH)
float
float
not valid
valid
t
d(DV)
t
d(QZ)
A0 to A1
CE
002aac692
t
su(A)
t
h(A)
t
su(CE_N)
t
h(CE_N)
WR
valid
t
w(WRH)
D0 to D7
(write)
t
su(Q)
t
h(Q)
t
w(WRL)