NXP Semiconductors
UM11216
PCA9420UK-EVM evaluation board user manual
UM11216
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User manual
Rev. 1.2 — 11 March 2020
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14 Layout Guideline
The following guidelines for PCA9420UK are arranged from most critical to least critical
priority:
•
Place ASYS input capacitor (C2) as close to ASYS and PGND as possible.
•
Place VBAT input capacitor (C3) as close to VBAT and PGND as possible. The input
capacitor delivers a high di/dt current pulse when the high-side MOSFET turns on. It
is essential that parasitic inductance in the power input traces be minimized for high
efficiency and reliability
•
Minimize the trace length from LX1, LX2’s output capacitor PGND1, PGND2 terminal
to the input capacitor’s GND terminal. This minimizes the area of the current loop when
the high-side MOSFET is conducting. Keep all sensitive signals, such as feedback
nodes, outside of these current loops with as much isolation as the design allows.
•
Minimize the trace impedance from LX1, LX2 to their respective inductor and from
each inductor to the output capacitor for LX1 and LX2. This minimizes the area of
each current loop and minimizes LX trace resistance and stray capacitance to achieve
optimal efficiency. Keep all sensitive signals, such as feedback nodes outside of these
current loops and away from the LX switching voltage with as much isolation as the
design allows.
•
Create a PGND plane on the 2nd layer of the PCB immediately below the power
components and bumps carrying high switching currents. This reduces parasitic
inductance in the traces carrying high currents and shields signals on inner PCB layers
from the switching waveforms on the top layer of the PCB.
•
Connect the feedback terminal (SW1_OUT, SW2_OUT) to the local output capacitors
for LX1 and LX2. The SW1_OUT and SW2_OUT connection to the local output
capacitors should be placed as close to the PCA9420UK as possible to minimize the
effects of voltage drop in the output trace connected to the load.
•
Create a small AGND island for the VIN bypass capacitors. Connect this AGND island
to the PCA9420UK PGND plane for LX1 and LX2 between the PGND terminals of the
SW1_OUT, SW2_OUT output capacitors. This results in the most accurate sensing of
the output voltage by the local feedback loop (OUT to AGND).
•
Each of the PCA9420UK bumps has approximately the same ability to remove heat
from the die. Connect as much metal as possible to each bump to minimize the θ
JA
associated with the PCA9420UK.