UM10346_1
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 01 — 2 November 2009
48 of 132
NXP Semiconductors
UM10346
LPC980/982 User manual
Table 37.
Timer/Counter x Control(TxCON - where x = 2, 3 or 4) bit description
Bit Symbol
Description
0
CP/NRLx Capture/Reload control. When set, captures occur on 1-to-0 transitions of TxEX (if EXENx is set). When
cleared, auto-reloads are performed on timer overflows or on negative transitions of TxEX (if EXENx is set).
1
C/NTx
Timer/Counter select. Cleared for Timer operation (input from PCLK). Set for Counter operation (input from
Tx input pin).
2
TRx
Timer x Run control bit. Set/cleared by software to turn Timer/Counter x on/off.
3
EXENx
When set, a falling edge on TxEX will trigger a capture or auto-reload.
4
PWMx
PWM control bit. When set, PWM function of corresponding channel is enabled, at the same time, Tx pin
outputs as a PWM output pin. Before enable PWM function, timer function and auto-reload function must be
selected.
5
TIENx
Timer x interrupt enable.
6
ENTx
Enable Tx pin output in 16-bit auto reload mode or PWM mode. When set, if 16-bit auto reload timer or
PWM mode is selected, Tx pin will be toggled upon the counter overflow.
7
PSELx
Tx pin output polarity selection. When 0, Tx pin outputs original polarity; when 1, Tx pin outputs inversed
polarity.
Table 38.
Timer/Counters Overflow and External Flags (TINTF, address CEh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
--
-
TF4
EXF4
TF3
EXF3
TF2
EXF2
Reset
x
x
0
0
0
0
0
0
Table 39.
Timer/Counters Overflow and External Flags (TINTF, address CEh) bit description
Bit Symbol
Description
0
EXF2
Timer 2 external flag. This bit is set when a capture or reload is triggered by a negative transition on T2EX
and EXEN2 is set. If the Timer 2 interrupt is enabled, setting this bit will cause an interrupt to the Xtimer
vector.
1
TF2
Timer 2 overflow flag. Set by hardware when Timer/Counter 2 overflows. If the Timer 2 interrupt is enabled,
setting this bit will cause an interrupt to the Xtimer vector. This bit is not cleared by hardware when the
processor calls the interrupt service routine.
2
EXF3
Timer 3 external flag. This bit is set when a capture or reload is triggered by a negative transition on T3EX
and EXEN3 is set. If the Timer 3 interrupt is enabled, setting this bit will cause an interrupt to the Xtimer
vector.
3
TF3
Timer 3 overflow flag. Set by hardware when Timer/Counter 3 overflows. If the Timer 3 interrupt is enabled,
setting this bit will cause an interrupt to the Xtimer vector. This bit is not cleared by hardware when the
processor calls the interrupt service routine.
4
EXF4
Timer 4 external flag. This bit is set when a capture or reload is triggered by a negative transition on T4EX
and EXEN4 is set. If the Timer 4 interrupt is enabled, setting this bit will cause an interrupt to the Xtimer
vector.
5
TF4
Timer 4 overflow flag. Set by hardware when Timer/Counter 4 overflows. If the Timer 4 interrupt is enabled,
setting this bit will cause an interrupt to the Xtimer vector. This bit is not cleared by hardware when the
processor calls the interrupt service routine.
6:7 -
Reserved
