UM10147_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 28 April 2008
67 of 134
NXP Semiconductors
UM10147
P89LPC952/954 User manual
If double buffering is enabled, TB8_n MUST be updated before SnBUF is written, as
TB8_n will be double-buffered together with SnBUF data. The operation described in the
Section 10.17 “Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)” on
page 65
becomes as follows:
1. The double buffer is empty initially.
2. The CPU writes to TB8_n.
3. The CPU writes to SnBUF.
4. The SnBUF/TB8_n data is loaded to the shift register and a Tx interrupt is generated
immediately.
5. If there is more data, go to 7, else continue on 6.
6. If there is no more data, then:
–
If DBISEL_n is logic 0, no more interrupt will occur.
–
If DBISEL_n is logic 1 and INTLO_n is logic 0, a Tx interrupt will occur at the
beginning of the STOP bit of the data currently in the shifter (which is also the last
data).
–
If DBISEL_n is logic 1 and INTLO_n is logic 1, a Tx interrupt will occur at the end of
the STOP bit of the data currently in the shifter (which is also the last data).
7. If there is more data, the CPU writes to TB8_n again.
8. The CPU writes to SnBUF again. Then:
–
If INTLO_n is logic 0, the new data will be loaded and a Tx interrupt will occur at
the beginning of the STOP bit of the data currently in the shifter.
–
If INTLO_n is logic 1, the new data will be loaded and a Tx interrupt will occur at
the end of the STOP bit of the data currently in the shifter.
9. Go to 4.
10. Note that if DBISEL_n is logic 1 and the CPU is writing to SnBUF when the STOP bit
of the last data is shifted out, there can be an uncertainty of whether a Tx interrupt is
generated already with the UART not knowing whether there is any more data
following.
10.19 Multiprocessor communications
UART modes 2 and 3 have a special provision for multiprocessor communications. In
these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is
stored in RB8_n. The UART can be programmed such that when the stop bit is received,
the serial port interrupt will be activated only if RB8_n = 1. This feature is enabled by
setting bit SM2_n in SnCON. One way to use this feature in multiprocessor systems is as
follows:
When the master processor wants to transmit a block of data to one of several slaves, it
first sends out an address byte which identifies the target slave. An address byte differs
from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With
SM2_n = 1, no slave will be interrupted by a data byte. An address byte, however, will
interrupt all slaves, so that each slave can examine the received byte and see if it is being
addressed. The addressed slave will clear its SM2_n bit and prepare to receive the data
bytes that follow. The slaves that weren’t being addressed leave their SM2_n bits set and
go on about their business, ignoring the subsequent data bytes.
