NXP Semiconductors P89LPC952, Руководство пользователя

Страница: 56 / 134

UM10147_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 28 April 2008 56 of 134
NXP Semiconductors
UM10147
P89LPC952/954 User manual
10. UARTs
The P89LPC952/954 has two enhanced UARTs that are compatible with the conventional
80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The
P89LPC952/954 does include an independent Baud Rate Generator for each UART. The
baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or
the independent Baud Rate Generator. In addition to the baud rate generation,
enhancements over the standard 80C51 UART include Framing Error detection, break
detect, automatic address recognition, selectable double buffering and several interrupt
options.
The UART can be operated in 4 modes, as described in the following sections.
10.1 Mode 0
Serial data enters and exits through RXDn. TXDn outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at
1
⁄
16
of the CPU clock
frequency.
10.2 Mode 1
10 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0), 8
data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in
RB8 in Special Function Register SnCON. The baud rate is variable and is determined by
the Timer 1 overflow rate or the Baud Rate Generator (see
Section 10.6 “Baud Rate
generator and selection” on page 57 ).
10.3 Mode 2
11 bits are transmitted (through TXDn) or received (through RXDn): start bit (logic 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is
transmitted, the 9th data bit (TB8 in SnCON) can be assigned the value of 0 or 1. Or, for
example, the parity bit (P, in the PSW) could be moved into TB8. When data is received,
Table 43. Real-time Clock Control register (RTCCON - address D1h) bit description
Bit Symbol Description
0 RTCEN Real-time Clock enable. The Real-time Clock will be enabled if this bit is logic 1.
Note that this bit will not power-down the Real-time Clock. The RTCPD bit
(PCONA.7) if set, will power-down and disable this block regardless of RTCEN.
1 ERTC Real-time Clock interrupt enable. The Real-time Clock shares the same
interrupt as the watchdog timer. Note that if the user configuration bit WDTE
(UCFG1.7) is logic 0, the watchdog timer can be enabled to generate an
interrupt. Users can read the RTCF (RTCCON.7) bit to determine whether the
Real-time Clock caused the interrupt.
2:4 - reserved
5 RTCS0 Real-time Clock source select (see Table 41 ).
6 RTCS1
7 RTCF Real-time Clock Flag. This bit is set to logic 1 when the 23-bit Real-time Clock
reaches a count of logic 0. It can be cleared in software.