UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
95 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
The overall connections to both comparators are shown in
. There are eight
possible configurations for each comparator, as determined by the control bits in the
corresponding CMPn register: CPn, CNn, and OEn. These configurations are shown in
.
When each comparator is first enabled, the comparator output and interrupt flag are not
guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt
should not be enabled during that time, and the comparator interrupt flag must be cleared
before the interrupt is enabled in order to prevent an immediate interrupt service.
Table 83.
Comparator Control register (CMP1 - address ACh, CMP2 - address ADh) bit
allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
CEn
CPn
CNn
OEn
COn
CMFn
Reset
x
x
0
0
0
0
0
0
Table 84.
Comparator Control register (CMP1 - address ACh, CMP2 - address ADh) bit
description
Bit Symbol
Description
0
CMFn
Comparator interrupt flag. This bit is set by hardware whenever the comparator
output COn changes state. This bit will cause a hardware interrupt if enabled.
Cleared by software.
1
COn
Comparator output, synchronized to the CPU clock to allow reading by software.
2
OEn
Output enable. When logic 1, the comparator output is connected to the CMPn pin
if the comparator is enabled (CEn = 1). This output is asynchronous to the CPU
clock.
3
CNn
Comparator negative input select. When logic 0, the comparator reference pin
CMPREF is selected as the negative comparator input. When logic 1, the internal
comparator reference, V
REF
, is selected as the negative comparator input.
4
CPn
Comparator positive input select. When logic 0, CINnA is selected as the positive
comparator input. When logic 1, CINnB is selected as the positive comparator
input.
5
CEn
Comparator enable. When set, the corresponding comparator function is enabled.
Comparator output is stable 10 microseconds after CEn is set.
6:7
-
reserved
