NXP Semiconductors P4080, Руководство пользователя, Страница: 45 / 60

P4080 Development System User’s Guide, Rev. 0
Freescale Semiconductor 45
Programming Model
“Dynamic” are those configuration pins that are only asserted during HRESET (these are also
processor-only configuration pins), while “Static” configuration pins remain constant as long as the system
power is operational.
7 Programming Model
This section covers general programming information to help guide the writing of board support packages.
7.1 ngPIXIS Registers
The ngPIXIS device contains several software accessible registers that are accessed from the base address
programmed for LCS3 (see
Section 5.1.5, “Local Bus” ). This table shows the register map of the ngPIXIS
device.
SW10 (1–2) zl_ca_v_sel[1:0] Static
(3–4) zl_cb_v_sel[1:0]
(5–6) zl_pl_v_sel[1:0]
7 n/a —
8 n/a —
Table 22. ngPIXIS Register Map
Base Address Offset Register Access Reset Section/Page
0x00 PX_ID—System ID register R 0x17 7.1.1/46
0x01 PX_ARCH—System architecture version register R 0x01 7.1.2/46
0x02 PX_SCVER—ngPIXIS version register R 0x02 7.1.3/47
0x03 PX_CSR—General control/status register R/W All zeros 7.1.4/48
0x04 PX_RST—Reset control register R/W All zeros 7.1.5/48
0x05 Reserved — — —
0x06 PX_AUX—Auxiliary register R/W All zeros 7.1.6/49
0x07 PX_SPD—Speed register R All zeros 7.1.7/50
0x08 PX_BRDCFG0—Board Configuration register 0 R/W 0x11 7.1.8/50
0x0A PX_ADDR—SRAM Address Register R/W All zeros 7.1.9/51
0x0B–0x0C Reserved — — —
0x0D PX_DATA—SRAM Data Register R/W Undefined 7.1.10/51
0x0E PX_LED—LED Data Register R/W All zeros 7.1.11/52
0x0F Reserved — — —
0x10 PX_VCTL—VELA Control Register R/W All zeros 7.1.12/52
Table 21. Configuration Switches (continued)
Group Switches Configuration Signals Class