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P4080 Development System User’s Guide, Rev. 0

Freescale Semiconductor

11

Architecture

5.1.1.1

Compatible DDR-3 Modules

The DDR interface of the P4080DS and the P4080 works with any JEDEC-compliant, 240-pin, DDR3
DIMM module. This table shows several DIMM modules that are believed to be compatible.

5.1.2

SerDes x18

The SerDes block provides high-speed serial communications interfaces for several internal devices. The
SerDes block provides 18 serial lanes that may be partitioned as shown in this table.

Note that the term ‘lane’ is used to describe the minimum number of signals needed to create a
bidirectional communications channel; in the case of PCI Express or Serial RapidIO, a lane consists of two
differential pairs, one for receive and one for transmit, or four in all.

, top down, shows three clocking banks: 1, 2, and 3. For Bank1, lanes A–B go to slot 1, C–D to slot

2, E–H go to slot 3, and I–J to the Aurora debug connector. For Bank 2, lanes A–D go to slot 4. For Bank
3, lanes A–D got to slot 5.

This figure shows an overview of Bank1.

Table 4. DDR-3 Modules

Mfg.

Part Number

Size

Ranks

ECC

Data Rate

Verified?

Notes

Elpida

EBJ21EE8BAFA-DJ-E

2 Gbytes

2

Y

1333

TBD

Or later revisions

Table 5. SerDes Lane Multiplexing/Configuration

Bank 1

Bank 2

Bank 3

A

B

C

D

E

F

G

H

I

J

A

B

C

D

A

B

C

D

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

14

16

17

SLOT 1

SLOT 2

SLOT 3

Aurora

Conn.

SLOT 4

SLOT 5

PCIe1

(5/2.5G)

PCIe3

(5/2.5G)

PCIe2

(5/2.5G)

Debug

(5/2.5G)

4× SGMII FM2

4× SGMII FM1

PCIe1

(5/2.5G)

PCIe3

(5/2.5G)

PCIe2

(5/2.5G)

Debug

(5/2.5G)

XAUI FM2

4× SGMII FM1

PCIe1

(5/2.5G)

PCIe3

(5/2.5G)

PCIe2

(5/2.5G)

Debug

(5/2.5G)

XAUI FM2

XAUI FM1

PCIe1
(2.5G)

PCIe3
(2.5G)

4× SGMII FM2

Debug

(2.5G)

XAUI FM2

4× SGMII FM1

PCIe1

(5/2.5G)

PCIe3

(5/2.5G)

—

sRIO2
(2.5G)

—

sRIO1
(2.5G)

Debug

(5/2.5G)

4× SGMII FM2

4× SGMII FM1

PCIe1

(5/2.5G)

PCIe3

(5/2.5G)

—

sRIO2
(2.5G)

—

sRIO1
(2.5G)

Debug

(5/2.5G)

XAUI FM2

4× SGMII FM1

PCIe1

(5/2.5G)

PCIe3

(5/2.5G)

—

sRIO2
(2.5G)

—

sRIO1
(2.5G)

Debug

(5/2.5G)

XAUI FM2

XAUI FM1

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Содержание P4080

Страница 1: ...part number The P4080DS is designed to the ATX form factor standard allowing it to be used in 2U rack mount chassis as well as in a standard ATX chassis The system is lead free and RoHS compliant Cont...

Страница 2: ...er channel 240 pin sockets that support standard JEDEC DIMMs Triple speed Ethernet USB controller One 10 100 1G port uses on board VSC8244 PHY in RGMII mode One USB ULPI Combo USB RJ45 stack Local bus...

Страница 3: ...nt VCore temperature monitoring and reconfiguration Clocks System clock SYSCLK switch settable to one of eight common settings in the interval 66 MHz 133 MHz Software settable in 1 MHz increments from...

Страница 4: ...ntrol PM Logic FPGA Local Bus Local Bus Emulator PromJet Emulator PromJet SYS PEX Clocks SGMII XAUI Riser Slot SPI 4 bit SD MMC 4 bit SD MMC Each riser supports 1 XAUI OR 4 SGMII using x4 lanes Three...

Страница 5: ...escale Semiconductor 5 Block Diagram and Placement This figure highlights more difficult to find connections that are commonly used Figure 2 Expedition Top View Notes I2C HEADERS AURORA and LEGACY COP...

Страница 6: ...uses Tek NextWave analyzer breakout cards No special MECC debug tap eSDHC Supports SDMedia cards and MMC cards SPI Supports standard and x4 devices Local Bus 1 bank of 16 bit 8 Mbyte 1 Gbyte Flash 64...

Страница 7: ...dded Use For general embedded hardware and or software development and evaluation purposes the P4080DS can be used just like an ordinary desktop computer Perpiherals and embedded storage can be connec...

Страница 8: ...rget reconfiguration VCTL GO 1 System is reconfigured target processor remains in reset This may take several milliseconds Download Target Download to target execution space Presumably the DDR and PCI...

Страница 9: ...interface includes all the necessary termination and I O power and is routed so as to achieve maximum performance on the memory bus eOpenPIC Section 5 1 10 eOpenPIC Interrupt Controller GPIO Section 5...

Страница 10: ...s to debug information on the MECC pins is possible with the use of a NextWave or equivalent DDR logic analyzer connector and the use of non ECC DDR modules 32 bit DDR3 interface mode is supported fro...

Страница 11: ...t 1 C D to slot 2 E H go to slot 3 and I J to the Aurora debug connector For Bank 2 lanes A D go to slot 4 For Bank 3 lanes A D got to slot 5 This figure shows an overview of Bank1 Table 4 DDR 3 Modul...

Страница 12: ...ic analyzer to analyze bus activity P4080 SD_TX RX 0 1 p n Mid bus probe PEX Slot 1 TX RX 0 1 p n REFCLK_SD1 p n 100 MHz Mid bus probe PEX Slot 2 TX RX 0 1 p n Mid bus probe PEX Slot 3 TX RX 0 3 p n M...

Страница 13: ...3 Configuration Note that the Mid bus probes are not on the development system but are available on the SGMII and XAUI riser cards The SD2 and SD3 clocking domains are separate clock generators P4080...

Страница 14: ...4080DS EC1 routes via ULPI to a USB PHY See Section 5 1 8 USB Interface for more information This table summarizes connections and routing This figure shows the general organization of the Ethernet sy...

Страница 15: ...for the IEEE 1588 precision time protocol PTP This facility works in tandem with the Ethernet controller to time stamp incoming packets This figure shows an overview of the IEEE 1588 block Figure 8 IE...

Страница 16: ...atched address pins and to buffer the data This figure shows an overview of the eLBC Figure 9 Local Bus Overview The P4080 can redirect boot fetches to the eLBC where it is routed to the device attach...

Страница 17: ...ardware implementation is not correct but the future system board re spin may incorporate a correct and supported implementation Table 7 Local Bus Chip Select Mapping Flash Selection cfg_lbmap 0 3 NOR...

Страница 18: ...ses of the Flash as shown in this figure Figure 10 Flash Address Toggle When LBMAP encoded bits A23 A25 of the Flash address are altered toggled as shown in Table 7 the Flash behaves normally or is sw...

Страница 19: ...are supported the latter using the SPI_CS_B 0 3 signals which can be reassigned as eSHDC_D 4 7 This figure shows the overall connections of the eSDHC block Figure 11 eSDHC Architecture The SDHC_DAT 4...

Страница 20: ...to communicate with various peripherals The P4080DS connects a conventional 16 Mbyte serial EEPROM to one chip select The remaining three chip selects are unused This figure shows the overall connect...

Страница 21: ...de the ID pin of the USB3300 can be controlled with ngPIXIS using the On The Go mode to switch to peripheral mode This requires a special adapter because a host expects the target device to be either...

Страница 22: ...dicated GPIO signals Table 8 Interrupt Connections Signal Names Connections IRQ0_B SLOT3 Sideband connector SGMII riser does not connect must use in band irq IRQ1_B DS3232 Realtime CLOCK and NVRAM IRQ...

Страница 23: ...and the Legacy COP SRST is mapped to the P4080 HRESET The P4080 HRESET is bi directional open drain signal but is not monitored by the ngPIXIS FPGA Basic system reset is mapped to the P4080 PORESET fo...

Страница 24: ...t to an arbitrary value the 3 bits in the PX_CLK register are not valid In this case the PX_AUX register is by convention set to the value of SYSCLK in MHz which is used in lieu of PX_CLK Note that th...

Страница 25: ...1 0x55 4KiB EEPROM Atmel AT24C64A or equivalent Stores ngPIXIS accessed configuration data Accessible while board is powered off Write protectable 1 0x56 4KiB EEPROM Atmel AT24C64A or equivalent Store...

Страница 26: ...DIMM Socket 2 Atmel AT24C02 Microchip MCP98242 or equivalent SPD EEPROM Type of device depends on the DIMM vendor the default Elpida device supplies an MCP98242 2 0x68 Real time clock DS3232 Optional...

Страница 27: ...easurement These pins are connected to the ADT7461 thermal monitor which allows direct reading of the temperature of the die and is accurate to 1 C This figure shows the thermal management scheme for...

Страница 28: ...ated at this time based on historical precedents and estimated power requirements These figures show the power architecture for the P4080 as implemented on the P4080DS Figure 18 P4080DS Power Architec...

Страница 29: ...Development System User s Guide Rev 0 Freescale Semiconductor 29 Architecture Figure 19 P4080DS Power Architecture for P4080 Part 2of 3 Figure 20 P4080DS Power Architecture for P4080 Part 3 of 3 P4080...

Страница 30: ...ween the BGA pads and the power and ground planes In particular the SMD capacitors should have pads directly attached to the via ring or within it if the PCB costs are not prohibitive 5 2 System Contr...

Страница 31: ...a transparent manner RESETSEQ Collects various reset power good signals and starts the global reset sequencer REGRESETS Drives resets from the sequencer from register based software control or from VE...

Страница 32: ...ed With COP not attached it is critical that reset does indeed assert TRST The COP core manages these modal operations 5 2 2 RESETSEQ RESETSEQ collects various reset power good signals and starts the...

Страница 33: ...ins during a system restart 5 2 8 OCM The off line configuration manager OCM is a small microprocessor GMSA that contains an embedded CPU core 8 Kbyte SRAM and I O peripherals UART I2 C GPIO and timer...

Страница 34: ...ower planes in the P4080DS PCB stackup The 12 V power from the standard ATX header is treated as separate from the ATX 12V power which supplies a large amount of current and is referred to as VCC_12V_...

Страница 35: ...on Switches Of particular interest is the PMBus capabilities of the ZL2006 the P4080DS uses hardware configuration pins to set the nominal voltage to 1 10 V but using PMBus commands nearly any paramet...

Страница 36: ...es Power XVDD is a filtered copy of the DDR power GVDD There is a backup LDO as an alternative source of XVDD Filtering is the primary choice while the LDO is for experimentation SVDD is a filtered co...

Страница 37: ...ide Rev 0 Freescale Semiconductor 37 Architecture GTXCLK P4080 EC_GTX_CLK125 VSC8244 XTAL1 125 MHz UPHYCLK USB PHY clock 26 000 MHz LVTTL Table 15 P4080DS Clock Requirements continued Clock Destinatio...

Страница 38: ...ot shown Figure 24 P4080DS Clock Architecture SD1 CLK PEX Slot 1 PEX 1 tap CLK14M ICS9FG108 100 MHz XOSC VSC8244 ngPIXIS PEX Slot 2 14 318 MHz 125 MHz MPC94551 ICS8304 P4080 RTC GTXCLK SD2 CLK hot XOS...

Страница 39: ...ter parameter was chosen 5 5 System Reset The P4080DS ngPIXIS contains a reset sequencer used to properly manage the orderly bring up of the system this is not the same as the power sequencer which is...

Страница 40: ...the P4080 can initialize internal registers such as SWx and ENx to allow a board to configure itself for the next restart termed self shmoo or self characterization A third option allows the ngPIXIS...

Страница 41: ...ized as in Section 6 1 1 1 Bypass If the system is not in self shmoo mode the OCM loads values from the SW 1 8 and EN 1 8 registers from the I2C based EEPROM storage at device address 0x55 This device...

Страница 42: ...ory configuration mode the OCM is still running code The target system may communicate with it via message passing see Section 5 2 8 OCM for details 6 1 1 3 Interactive In interactive configuration mo...

Страница 43: ...gned and only an FPGA has changed See the P4080DS Configuration Sheet which helps configure the system to a default configuation and has more detail as to the functionality of the these switches It is...

Страница 44: ...vdd_ca 0 1 5 6 vdd_cb 0 1 7 vdd_cb_en 8 vdd_povdd_en SW7 1 4 lbmap 0 3 Static 5 spare6 6 spare7 7 spare8 8 rstreq_en Static SW8 1 spare1 2 i2c_rcw_wp Static 3 flash_wp_b 4 id_wp 5 aurora_clk_en 6 pov...

Страница 45: ...sel 1 0 7 n a 8 n a Table 22 ngPIXIS Register Map Base Address Offset Register Access Reset Section Page 0x00 PX_ID System ID register R 0x17 7 1 1 46 0x01 PX_ARCH System architecture version register...

Страница 46: ...hitectural change because a CFI compliant Flash programmer should be able to handle such a change 0x11 PX_VSTAT VELA Status Register R All zeros 7 1 13 53 0x13 Reserved 0x14 PX_OCMCSR OCMCSR Register...

Страница 47: ...uted Because the FPGA image is generally designed to work on one or more board versions there is no correlation between the two Offset 0x00 Access Read only 0 7 R VER W Reset All zeros Figure 27 Archi...

Страница 48: ...one of several inputs for mapping to internal signal esig which in turn may be connected to special outputs see PIX_CSR EVEDEST 000 esig event_b 001 esig trig_out 010 esig evt_b 2 011 esig evt_b 3 11...

Страница 49: ...t sources PX_AUX preserves its value between Aurora COP or watchdog initiated resets Table 27 PX_RST Field Descriptions Bits Name Description 0 ALL Allows the entire system to be reset 0 A full system...

Страница 50: ...y this register may be changed at any time Offset 0x07 Access Read only 0 4 5 7 R SYSCLK W Reset 0 0 0 0 0 n n n Figure 32 Speed Status Register PX_SPD Table 29 PX_SPD Field Descriptions Bits Name Des...

Страница 51: ...ed to read or write to an internal 256 byte SRAM array Though reset upon initial power activation or by chassis reset sources PX_DATA preserves its value between COP or watchdog initiated resets 5 6 R...

Страница 52: ...cription 0 7 DATA Contents of SRAM array as indexed by PX_ADDR Offset 0x0E Access Read Write 0 7 R LED W Reset All zeros Figure 36 LED Data Register PX_LED Table 33 PX_LED Field Descriptions Bits Name...

Страница 53: ...on Note Note that the default value of PWROFF is zero so that normal operations do not interfere with the power switches Setting PWROFF to 1 overrides any user or APM initiated power switch event 7 GO...

Страница 54: ...t a message has been processed 1 U0 Unassigned values 2 5 DBGSEL Selects information to provide in the GMDBG register 6 U1 Unassigned values 7 MSG 0 No message is present 1 Signals OCM software that a...

Страница 55: ...y of any other watchdog timers such as those within the P4080 Offset 0x16 Access Read Write 0 7 R DATA W Reset All zeros Figure 41 GMSA Debug Register PX_GMDBG Table 38 PX_GMDBG Field Descriptions Bit...

Страница 56: ...er 26 bits x 30 ns interval 2 01326592 seconds Where the upper 8 bits represent seconds decimal value of the 8 bit field x 2 01326592sec 2 01326592sec Some examples values for PX_WATCH register values...

Страница 57: ...ores important data about the Expedition system including the following Board ID Errata level as shipped Manufacturing date Offset 0x20 0x22 0x24 Access Read Write 0 1 2 3 4 5 6 7 R SWx 1 SWx 2 SWx 3...

Страница 58: ...documents Table 44 Document Revision History Rev Number Date Substantive Change s 0 07 2011 Initial public release Table A 1 Useful References Topic Reference System design P4080 QorIQ Integrated Proc...

Страница 59: ...ts officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of pe...

Страница 60: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information NXP P4080DS PC...

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