Memory Management Unit (MMU) - The Memory Management Unit is similar to the Memory Protection unit in that it
allows memory regions to be protected from being accessed by certain cores, protected from being modified, and for
enabling/disabling of the cache for that memory region. However, it also supports the capability of remapping a logical (or
virtual) memory address into a physical hardware memory address, including the capability to map addresses based on a
Process ID. The MMU is much more complicated than the MPU, this is only a brief summary of the MMU capabilities. For
more information about the MMU, see a core reference manual or device reference manual that supports the MMU.
End-to-End Error Correction Coding (e2eECC) - End-to-end (e2e) Error Correction Coding (ECC) provides an additional
layer of safety by including ECC on all bus transactions. The ECC for the transfer is generated on the transmitting end of the
transaction and checked at the receiving end. e2eECC is an optional feature that can be implemented with the core and
system interfaces.
Cross-Bar (XBAR) interface - In general, the e200zx cores have traditionally implemented a 64-bit bus interface to the
Cross-Bar switch. On the newer e200zx cores, the instruction bus interface remains 64-bit, however, the data load/store bus
on some versions of the cores are implemented with a 32-bit interface to save power and die area (cost).
Local Data Memory (DTCM) - Some cores support a fast local data memory (SRAM). This is sometimes referred to as a
tightly coupled memory (DTCM). The size of this SRAM is definable for a given core variant. Not all devices implement
local memory. The local data memory allows for fast access of variables that are required frequently by a single core.
Local Instruction Memory (ITCM) - Some cores support a fast local instruction memory (SRAM). This is sometimes
referred to as a tightly coupled memory (ITCM). The size of this SRAM is definable for a given core variant. Not all devices
implement local memory. The local instruction memory can be loaded with frequently executed software routines, this is
similar to the concept of locking some regions of cache for frequently used subroutines or functions.
Data Cache (D-Cache) - Data cache allows fast access to recently used data from the load/store bus from memory space
outside of the core complex, typically the device internal flash or external
1
(to the device) memory. Different sizes of D-
Cache can be instantiated (as defined for a device) in a particular core.
Instruction Cache (I-Cache) - Instruction cache allows fast access to recently loaded instructions from memory (typically
flash). Different sizes of I-Cache can be instantiated (as defined for a device) in a particular core.
2.3 e200zx debug options
As with other features of the core, the debug options can be determined by the definition of the device requirements. These
allow different kinds of support depending on the requirements of the overall system. These options are shown in the
following table. Each of the options is then explained.
Table 6. e200zx cores debug feature options
Device
Revision
Instantiation
Core Name
Nexus class support
Timestamp
Nexus Port Width (MDO)
JTAG Nexus State
Machine Reset
DQM DQTAG packet type
e200z210 based cores
Table continues on the next page...
1. Not all devices support an external bus.
Differences between MPC57xx e200zx cores
Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013
Freescale Semiconductor, Inc.
7
