NXP Semiconductors MPC5746R, Техническое описание

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Table 28. Device power supply integration (continued)
Symbol Parameter Conditions
Value
1
Unit
Min Typ Max
C
HV_ADC_SD
Minimum V
DD_HV_ADV_SD
external
capacitance
, 7
1 2.2 — µF
1. See the above figure for capacitor integration.
2. Recommended X7R or X5R ceramic low ESR capacitors, ±15% variation over process, voltage, temperature, and aging.
3. Each V
DD_LV
pin requires both a 47nF and 0.01µF capacitor for high-frequency bypass and EMC requirements. Remaining
capacitance to meet minimum CLV requirement should be placed near the emitter of NPN ballast (if using internal
regulation mode), or it should be evenly distributed across VDD_LV pins (if using external regulation mode).
4. Each V
DD_HV_PMC
pin requires both a 47nF and 0.01µF capacitor for high-frequency bypass and EMC requirements.
5. The recommended flash regulator composition capacitor is 1.5µF typical X7R or X5R, with -50% and +35% as min and
max. This puts the min cap at 0.75 µF.
6. For noise filtering it is recommended to add high frequency bypass capacitors of three each 0.1 µF and three each 1nF
between V
DD_HV_ADV_SAR
and V
SS_HV_ADV_SAR
. These capacitors need to be placed very close to the MCU pins/balls to
have minimum PCB routing between pin/ball and the capacitors.
7. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF between V
DD_HV_ADV_SD
and
V
SS_HV_ADV_SD
.
16.1.3 Regulator example for the NJD2873 transistor
VDD_HV_PMC
VRC_CTL
VDD_LV
VSS
VRC_CTL capacitor: may or
may not be required
MCU
Mandatory decoupling capacitor
network
C1
The bypass transistor
MUST be operated out
of saturation region.
Figure 18. Regulator example
Power management PMC POR LVD sequencing
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
50 NXP Semiconductors