NXP Semiconductors MPC5602S, Справочное руководство

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Memory Protection Unit (MPU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 883
24.1.2 Features
The Memory Protection Unit implements a two-dimensional hardware array of memory region descriptors
and the crossbar slave AHB ports to continuously monitor the legality of every memory reference
generated by each bus master in the system. The feature set includes:
• Support for 12 memory region descriptors, each 128 bits in size
— Specification of start and end addresses provide granularity for region sizes from 32 bytes to
4 GB
— Access control definitions: 2 bus masters (processor cores) support the traditional {read, write,
execute} permissions with independent definitions for supervisor and user mode accesses
— Automatic hardware maintenance of the region descriptor valid bit removes issues associated
with maintaining a coherent image of the descriptor
— Alternate memory view of the access control word for each descriptor provides an efficient
mechanism to dynamically alter only the access rights of a descriptor
— For overlapping region descriptors, priority is given to permission granting over access
denying as this approach provides more flexibility to system software. See Section 24.3.2,
Putting It All Together and AHB Error Terminations , for details and Section 24.5, Application
information , for an example.
• Support for 3 AHB slave port connections: flash controller, system ram controller and IPS
peripherals bus
— MPU hardware continuously monitors every AHB slave port access using the preprogrammed
memory region descriptors
— An access protection error is detected if a memory reference does not hit in any memory region
or the reference is flagged as illegal in all memory regions where it does hit. In the event of an
access error, the AHB reference is terminated with an error response and the MPU inhibits the
bus cycle being sent to the targeted slave device.
— 64-bit error registers, one for each AHB slave port, capture the last faulting address, attributes
and “detail” information
• Global MPU enable/disable control bit provides a mechanism to easily load region descriptors
during system startup or allow complete access rights during debug with the module disabled
24.1.3 Modes of operation
The MPU module does not support any special modes of operation. As a memory-mapped device located
on the platform’s high-speed system bus, it responds based strictly on the memory addresses of the
connected system buses. The IPS bus is used to access the MPU’s programming model and the memory
protection functions are evaluated on a reference-by-reference basis using the addresses from the AHB
system bus port(s).
Power dissipation is minimized when the MPU’s global enable/disable bit is cleared
(MPU_CESR[VLD] = 0).