NXP Semiconductors MPC5602S, Справочное руководство

Страница: 512 / 1344

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
510 Freescale Semiconductor
• All IPS reads require two wait-states, and IPS writes three wait-states, again viewed from the
system bus data phase
• All IPS accesses are 32 bits in size
Table 15-29 presents a peak transfer rate comparison, measured in megabytes per second. In this table, the
Platform_SRAM-to-Platform_SRAM transfers occur at the native platform datapath width, that is, either
32- or 64-bits per access. For all transfers involving the IPS bus, 32-bit transfer sizes are used. In all cases,
the transfer rate includes the time to read the source plus the time to write the destination.
The second performance metric is a measure of the number of DMA requests which can be serviced in a
given amount of time. For this metric, it is assumed the peripheral request causes the channel to move a
single IPS-mapped operand to/from the platform SRAM. The same timing assumptions used in the
previous example apply to this calculation. In particular, this metric also reflects the time required to
activate the channel. The DMA design supports the following hardware service request sequence:
• Cycle 1: ipd_req[n] is asserted
• Cycle 2: The ipd_req[n] is registered locally in the DMA module and qualified (TCD.start bit
initiated requests start at this point with the registering of the IPS write to TCD word7)
• Cycle 3: Channel arbitration begins
• Cycle 4: Channel arbitration completes. The transfer control descriptor local memory read is
initiated.
• Cycle 5–6: The first two parts of the activated channel’s TCD is read from the local memory. The
memory width to the DMA engine is 64 bits, so the entire descriptor can be accessed in four cycles.
• Cycle 7: The first AMBA-AHB read cycle is initiated, as the third part of the channel’s TCD is read
from the local memory. Depending on the state of the platform’s crossbar switch, arbitration at the
system bus may insert an additional cycle of delay here.
• Cycle 8–?: The last part of the TCD is read in. This cycle represents the first data phase for the read,
and the address phase for the destination write.

The exact timing from this point is a function of the response times for the channel’s read and write
accesses. In this case of an IPS read and a platform SRAM write, the combined data phase time is
4 cycles. For an SRAM read and IPS write, it is 5 cycles.
Table 15-29. DMA peak transfer rates [MB/s]
Platform Speed,
Width
Platform SRAM-to-
Platform SRAM
32-bit IPS-to-
Platform SRAM
Platform SRAM-to-
32-bit IPS
66.7 MHz, 32-bit 133.3 66.7 53.3
66.7 MHz, 64-bit 266.7 66.6 53.3
83.3 MHz, 32-bit 166.7 83.3 66.7
83.3 MHz, 64-bit 333.3 83.3 66.7
100.0 MHz, 32-bit 200.0 100.0 80.0
100.0 MHz, 64-bit 400.0 100.0 80.0
133.3 MHz, 32-bit 266.7 133.3 106.7
133.3 MHz, 64-bit 533.3 133.3 106.7
150.0 MHz, 32-bit 300.0 150.0 120.0
150.0 MHz, 64-bit 600.0 150.0 120.0