NXP Semiconductors MPC5566, Справочное руководство

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Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 21-29
21.4.5.5.1 Slow Data Tolerance
Figure 21-19 shows how much a slow received frame can be misaligned without causing a noise error or
a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
Figure 21-19. Slow Data
For an 8-bit data character, data sampling of the stop bit takes the receiver RT clock 151 clock cycles, as
is shown below:
With the misaligned character shown in Figure 21-19 , the receiver counts 151 RT cycles at the point when
the count of the transmitting device is 9 bit times x 16 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data
character with no errors is 4.63%, as is shown below:
For a 9-bit data character, data sampling of the stop bit takes the receiver 167 RT cycles, as is shown below:
With the misaligned character shown in Figure 21-19 , the receiver counts 167 RT cycles at the point when
the count of the transmitting device is 10 bit times x 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is 4.19%, as is shown below:
RT1
Receiver
RT clock
RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16
MSB STOP
Data samples
9 bit times 16 RT cycles 7 RT cycles +
×
151 RT cycles =
151 – 144
151
--------------------------
100
×
4.63% =
10 bit times 16 RT cycles 7 RT cycles +
×
167 RT cycles =
167 – 160
167
--------------------------
100
×
4.19% =