At any time, an active edge on the RxD serial data input pin causes the
UART_S2[RXEDGIF] flag to set. The UART_S2[RXEDGIF] flag is cleared by writing a
1 to it. This function depends on the receiver being enabled (UART_C2[RE] = 1).
33.4.5 Baud rate tolerance
A transmitting device may operate at a baud rate below or above that of the receiver.
Accumulated bit time misalignment can cause one of the three stop bit data samples
(RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the
RT8, RT9, and RT10 samples are not all the same logical values. A framing error will
occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9,
and RT10 stop bit samples are a logic zero.
As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid
falling edge within the frame. Resynchronization within frames will correct a
misalignment between transmitter bit times and receiver bit times.
33.4.5.1 Slow data tolerance
shows how much a slow received frame can be misaligned without causing a
noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives
in time for the stop bit data samples at RT8, RT9, and RT10.
MSB
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT11
RT12
RT13
RT14
RT15
RT16
DATA
SAMPLES
RECEIVER
RT CLOCK
STOP
Figure 33-4. Slow data
For an 8-bit data and 1 stop bit character, data sampling of the stop bit takes the receiver
9 bit times x 16 RT 10 RT cycles =154 RT cycles.
With the misaligned character shown in
, the receiver counts 154 RT cycles at
the point when the count of the transmitting device is 9 bit times x 16 RT 3 RT
cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of
a slow 8-bit data and 1 stop bit character with no errors is:
((154 - 147) / 154) x 100 = 4.54%
Chapter 33 Universal asynchronous receiver/transmitter (UART1 and UART2)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc.
667
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