NXP Semiconductors MIMXRT1160, Руководство по разработке аппаратного обеспечения

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Table 11. ROM Bootloader Peripheral PinMux (continued)
Peripheral Instance Port (IO function) PAD Mode Note
2 USDHC2_CD_B GPIO_AD_26 ALT11
USDHC2_WP GPIO_AD_27 ALT11
USDHC2_VSELECT GPIO_AD_28 ALT11
USDHC2_DATA3 GPIO_SD_B2_00 ALT0
USDHC2_DATA2 GPIO_SD_B2_01 ALT0
USDHC2_DATA1 GPIO_SD_B2_02 ALT0
USDHC2_DATA0 GPIO_SD_B2_03 ALT0
USDHC2_CLK GPIO_SD_B2_04 ALT0
USDHC2_CMD GPIO_SD_B2_05 ALT0
USDHC2_RESET_B GPIO_SD_B2_06 ALT0
USDHC2_DATA4 GPIO_SD_B2_08 ALT0
USDHC2_DATA5 GPIO_SD_B2_09 ALT0
USDHC2_DATA6 GPIO_SD_B2_10 ALT0
USDHC2_DATA7 GPIO_SD_B2_11 ALT0
FlexSPI1 1 FLEXSPI1_B_DATA
3 GPIO_SD_B2_00 ALT1
QSPI memory attached to
FlexSPI is a primary boot option.
Refer to Serial NOR Flash
Boot via FlexSPI in Reference
Manual for more information.
The ROM will read the 512-
byte FlexSPI NOR configuration
parameters described in FlexSPI
Serial NOR Flash Boot Operation
Reference Manual using the non-
italicized pins.
Note: These pins are a secondary
pinout option for FlexSPI serial
NOR flash boot
FLEXSPI1_B_DATA
2 GPIO_SD_B2_01 ALT1
FLEXSPI1_B_DATA
1 GPIO_SD_B2_02 ALT1
FLEXSPI1_B_DATA
0 GPIO_SD_B2_03 ALT1
FLEXSPI1_B_SCLK GPIO_SD_B2_04 ALT1
FLEXSPI1_B_DQS GPIO_SD_B1_05 ALT8
FLEXSPI1_B_SS0_B GPIO_SD_B1_04 ALT8
FLEXSPI1_B_SS1_B GPIO_SD_B1_03 ALT9
FLEXSPI1_A_DQS GPIO_SD_B2_05 ALT1
FLEXSPI1_A_SS0_B GPIO_SD_B2_06 ALT1
FLEXSPI1_A_SS1_B GPIO_SD_B1_02 ALT9
FLEXSPI1_A_SCLK GPIO_SD_B2_07 ALT1
FLEXSPI1_A_DATA
0 GPIO_SD_B2_08 ALT1
FLEXSPI1_A_DATA
1 GPIO_SD_B2_09 ALT1
Table continues on the next page...
NXP Semiconductors
Boot, reset, and miscellaneous
Hardware Development Guide for the MIMXRT1160/1170 Processor , Rev. 2, 09/2021
User Guide 14 / 24