NXP Semiconductors MCF5253, Справочное руководство

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Bus Operation
MCF5253 Reference Manual, Rev. 1
8-6 Freescale Semiconductor
terminate in an error. If a match is found for any chip selects or DRAM, the bus cycle will be executed on
the external bus. Chip select accesses follow timing diagrams given in this section. DRAM accesses are
different. They are described in the section on the DRAM controller.
Table 8-5 shows the type of access as a function of match in various memory space programming registers.
Basic operation of the MCF5253 bus is a three-clock bus cycle. During the first clock, the address is
driven. CSx is asserted at the falling edge of the clock to indicate that address and attributes are valid and
stable. Data and TA are sampled during the second clock of a bus-read cycle. TA is generated internally in
the chip select module.
During a read, the external device provides data and is sampled at the rising edge at the end of the second
bus clock. This data is concurrent with TA, which is also sampled at the rising edge of the clock. During
a write, the MCF5253 drives data from the rising clock edge at the end of the first clock to the rising clock
edge at the end of the bus cycle.
Users can add wait states between the first and second clocks by delaying the assertion of TA. This refers
to internal transfers only and not the write cycles. This is done by programming the relevant chip select
registers. If “0000” is programmed in the WS field of the relevant chip select register, a no wait cycle
results. If
n is programmed in the WS field, n wait cycles will result. The last clock of the bus cycle uses
what would be an idle clock between cycles to provide hold time for address and write data. Figure 8-4
and Figure 8-6 show the basic read and write operations.
8.5.2 Read Cycle
The Read cycle as shown in Figure 8-3 , will occur if the wait cycle field (WS) in the Chip Select Control
Register (CSR) is programmed to value “0000”. The CS low time is increased with n clocks if n is
programmed into the WS field.
During a read cycle, the MCF5253 receives data from memory or from a peripheral device. The read cycle
flowchart is shown in
Figure 8-3 while the read cycle timing diagram is shown in Figure 8-4 .
Table 8-5. Accesses by Matches
KRAM
Matches
SBC 2
Matches
SBC 1
Matches
Number of
Chip Selects
Register
Matches
Number of
DRAM
Controller
Register
Matches
Type of Access
yes any any any any on-chip SRAM
no yes any any any SBC 2
no no yes none none SBC 1
no no no single none as defined by Chip-Select control register
no no no none single as defined by DRAM control register
no no no none none Undefined
All other combinations Undefined