NXP Semiconductors MC9S12VRP64, Руководство владельца

Страница: 453 / 555

64 KByte Flash Module (S12FTMRG64K4KV2)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 453
18.3.2.8 Flash Error Status Register (FERSTAT)
The FERSTAT register reflects the error status of internal Flash operations.
All flags in the FERSTAT register are readable and only writable to clear the flag.
3
MGBUSY
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller
.
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0)
2
RSVD
Reserved Bit — This bit is reserved and always reads 0
.
1–0
MGSTAT[1:0]
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
is detected during execution of a Flash command or during the Flash reset sequence. See Section 18.4.6,
“Flash Command Description ,” and Section 18.6, “Initialization ” for details.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
DFDIF SFDIF
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 18-12. Flash Error Status Register (FERSTAT)
Table 18-16. FERSTAT Field Descriptions
Field Description
1
DFDIF
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
returning invalid data was attempted on a Flash block that was under a Flash command operation.
1
The DFDIF
flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
2
0 No double bit fault detected
1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command
running
1
The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either
single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data
attempted while command running) is indicated when both SFDIF and DFDIF flags are high.
2
There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after
a flash memory read before checking FERSTAT for the occurrence of ECC errors.
0
SFDIF
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash
command operation.
1
The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on
SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted
while command running
Table 18-15. FSTAT Field Descriptions (continued)
Field Description