NXP Semiconductors MC9S08QL4, Справочное руководство

Страница: 121 / 240

MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 121
Chapter 10
Analog-to-Digital Converter (S08ADC12V1)
10.1 Introduction
The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation
within an integrated microcontroller system-on-chip.
10.1.1 ADC Clock Gating
The bus clock to the ADC can be gated on and off using the ADC bit in SCGC1. This bit is set after any
reset, which enables the bus clock to this module. To conserve power, the ADC bit can be cleared to disable
the clock to this module when not in use. See
Section 5.7, Peripheral Clock Gating for details.
10.1.2 Module Configurations
This section provides device-specific information for configuring the ADC on MC9S08QL8 series.
10.1.2.1 Analog Supply and Voltage Reference Connections
The MC9S08QL8 series V
DDA/VREFH
and V
SSA/VREFL
pins are double bonded to V
DD
and V
SS
, in the
20-pin and 16-pin packages.
10.1.2.2 Configurations for Stop and Low Power Modes
The ADC, if enabled, must be configured to use the asynchronous clock source, ADACK, to meet the ADC
minimum frequency requirements. To convert the internal bandgap channel (AD27), the LVD must be
enabled in stop mode (LVDE and LVDSE bits set in the SPMSC1 register). The bandgap channel cannot
be converted in low power run or low power wait modes.
10.1.2.3 Channel Assignments
The ADC channel assignments for the MC9S08QL8 series devices are shown in Table 10-1 . Reserved
channels convert to an unknown value.
Table 10-1. ADC Channel Assignment
ADCH Channel Input Pin Control ADCH Channel Input Pin Control
00000 AD0 PTA0/ADP0 ADPC0 10000 AD16 V
REFL
N/A
00001 AD1 PTA1/ADP1 ADPC1 10001 AD17 V
REFL
N/A
00010 AD2 PTA2/ADP2 ADPC2 10010 AD18 V
REFL
N/A