NXP Semiconductors MC9S08PA4, Справочное руководство

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DBG_FH field descriptions
Field Description
F[15:8] FIFO High Data Bits
The FIFO High data bits provide access to bits [15:8] of data in the FIFO. This register is not used in event
only modes and will read a $00 for valid FIFO words.
19.3.8 Debug FIFO Low Register (DBG_FL)
NOTE
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 3010h base + 7h offset = 3017h
Bit 7 6 5 4 3 2 1 0
Read F[7:0]
Write
Reset
0 0 0 0 0 0 0 0
DBG_FL field descriptions
Field Description
F[7:0] FIFO Low Data Bits
The FIFO Low data bits contain the least significant byte of data in the FIFO. When reading FIFO words,
read DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the FIFO pointers to
advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX and
DBGFH so it is not necessary to read them before reading DBGFL.
Chapter 19 Debug module (DBG)
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
NXP Semiconductors 379