NXP Semiconductors MC9S08LG16, Справочное руководство

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Chapter 13 Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 311
The TPM channels are programmable independently as input capture, output compare, or edge-aligned
PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When
the TPM is configured for CPWMs (the counter operates as an up/down counter) input capture, output
compare, and EPWM functions are not practical.
16.2 Signal Description
Table 16-2 shows the user-accessible signals for the TPM. The number of channels are varied from one to
eight. When an external clock is included, it can be shared with the same pin as any TPM channel;
however, it could be connected to a separate input pin. Refer to the I/O pin descriptions in full-chip
specification for the specific chip implementation.
16.2.1 Detailed Signal Descriptions
16.2.1.1 EXTCLK — External Clock Source
The external clock signal can share the same pin as a channel pin, however the channel pin can not be used
for channel I/O function when external clock is selected. If this pin is used as an external clock
(CLKSB:CLKSA = 1:1), the channel can still be configured to output compare mode therefore allowing
its use as a timer (ELSnB:ELSnA = 0:0).
For proper TPM operation, the external clock frequency must not exceed one-fourth of the bus clock
frequency.
16.2.1.2 TPMxCHn — TPM Channel n I/O Pins
The TPM channel does not control the I/O pin when ELSnB:ELSnA or CLKSB:CLKSA are cleared so it
normally reverts to general purpose I/O control. When CPWMS is set and ELSnB:ELSnA are not cleared,
all TPM channels are configured for center-aligned PWM and the TPMxCHn pins are all controlled by
TPM. When CPWMS is cleared, the MSnB:MSnA control bits determine whether the channel is
configured for input capture, output compare, or edge-aligned PWM.
When a channel is configured for input capture (CPWMS = 0, MSnB:MSnA = 0:0, and
ELSnB:ELSnA
≠
0:0), the TPMxCHn pin is forced to act as an edge-sensitive input to the TPM.
ELSnB:ELSnA control bits determine what polarity edge or edges trigger input capture events. The
channel input signal is synchronized on the bus clock. This implies the minimum pulse width—that can
Table 16-2. Signal Properties
Name Function
EXTCLK
1
1
The external clock pin can be shared with any channel pin. However, depending upon full-chip
implementation, this signal could be connected to a separate external pin.
External clock source that is selected to drive the TPM counter.
TPMxCHn
2
2
n = channel number (1–8)
I/O pin associated with TPM channel n.