NXP Semiconductors MC9S08LG16, Справочное руководство

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Chapter 16 Internal Clock Source (S08ICSV3)
MC9S08LG32 MCU Series, Rev. 5
238 Freescale Semiconductor
In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock source.
The FLL clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency
to the FLL factor times the external reference frequency, as selected by the RDIV bits, so that the
ICSLCLK will be available for BDC communications, and the external reference clock is enabled.
11.4.1.6 FLL Bypassed External Low Power (FBELP)
The FLL bypassed external low-power (FBELP) mode is entered when all the following conditions occur:
• CLKS bits are written to 10.
• IREFS bit is written to 0.
• BDM mode is not active and LP bit is written to 1.
In FLL bypassed external low-power mode, the ICSOUT clock is derived from the external reference
clock source and the FLL is disabled. The ICSLCLK will be not be available for BDC communications.
The external reference clock source is enabled.
11.4.1.7 Stop
Stop mode is entered whenever the MCU enters a STOP state. In this mode, all ICS clock signals are static
except in the following cases:
ICSIRCLK will be active in stop mode when all the following conditions occur:
• IRCLKEN bit is written to 1
• IREFSTEN bit is written to 1
OSCOUT will be active in stop mode when all the following conditions occur:
• ERCLKEN bit is written to 1
• EREFSTEN bit is written to 1
11.4.2 Mode Switching
The IREF bit can be changed at anytime, but the actual switch to the newly selected clock is shown by the
IREFST bit. When switching between FLL engaged internal (FEI) and FLL engaged external (FEE)
modes, the FLL will begin locking again after the switch is completed.
The CLKS bits can also be changed at anytime, but the actual switch to the newly selected clock is shown
by the CLKST bits. If the newly selected clock is not available, the previous clock will remain selected.
The DRS bits can be changed at anytime except when LP bit is 1. If the DRS bits are changed while in
FLL engaged internal (FEI) or FLL engaged external (FEE), the bus clock remains at the previous DCO
range until the new DCO starts. When the new DCO starts the bus clock switches to it. After switching to
the new DCO the FLL remains unlocked for several reference cycles. Once the selected DCO startup time
is over, the FLL is locked. The completion of the switch is shown by the DRST bits.