NXP Semiconductors LPC84x, Руководство пользователя

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User manual Rev. 1.0 — 16 June 2017 477 of 515
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Chapter 28: LPC84x Analog comparator
28.5.4 Comparator outputs
The comparator output (conditioned by COMPSA bit) can be routed to an external pin.
When COMPSA is 0 and the comparator interrupt is disabled, the comparator can be
used with the bus clock disabled (
Table 146 “System clock control 0 register
(SYSAHBCLKCTRL0, address 0x4004 8080) bit description” ) to save power if the control
registers don’t need to be written.
The status of the comparator output can be observed through the comparator status
register bit.
The comparator output can be routed to the SCT via the switch matrix allowing to capture
the time of a voltage crossing or to count crossings in either or both directions. See
Section 28.3.1 “Connect the comparator output to the SCTimer/PWM” .
28.6 Register description
28.6.1 Comparator control register
This register enables the comparator, configures the interrupts, and controls the input
multiplexers on both sides of the comparator. All bits not shown in
Table 464 are reserved
and should be written as 0.
Table 463. Register overview: Analog comparator (base address 0x4002 4000)
Name Access Address
offset
Description Reset
value Reference
CTRL R/W 0x000 Comparator control register 0 Table 464
LAD R/W 0x004 Voltage ladder register 0 Table 465
Table 464. Comparator control register (CTRL, address 0x4002 4000) bit description
Bit Symbol Value Description Reset
value
2:0 - Reserved. Write as 0. 0
4:3 EDGESEL This field controls which edges on the comparator
output set the COMPEDGE bit (bit 23 below): 0
0x0 Falling edges
0x1 Rising edges
0x2 Both edges
0x3 Both edges
5 - Reserved. Write as 0. 0
6 COMPSA Comparator output control 0
0 Comparator output is used directly.
1 Comparator output is synchronized to the bus clock
for output to other modules.
7 - Reserved. Write as 0. 0