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UM10601

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2012. All rights reserved.

Preliminary user manual

Rev. 1.0 — 7 November 2012 

213 of 313

NXP Semiconductors

UM10601

Chapter 17: LPC800 SPI0/1

17.6.3 SPI Status register

The STAT register provides SPI status flags for software to read, and a control bit for 
forcing an end of transfer. Flags other than read-only flags may be cleared by writing ones 
to corresponding bits of STAT.

STAT contains 2 error flags. RXOV and TXUR. These are receiver overrun and transmit 
underrun, respectively. If either of these errors occur during operation, the SPI should be 
disabled, then re-enabled in order to make sure all internal states are cleared before 
attempting to resume operation.

In this register, the following notation is used: RO = Read-only, W1 = write 1 to clear..

 

Table 191. SPI Status register (STAT, addresses 0x4005 8008 (SPI0) , 0x4005 C008 (SPI1)) bit description

Bit

Symbol

Description

Reset 
value

Access

[1]

0

RXRDY

Receiver Ready flag. When 1, indicates that data is available to be read from 
the receiver buffer. Cleared after a read of the RXDAT register.

0

RO

1

TXRDY

Transmitter Ready flag. When 1, this bit indicates that data may be written to 
the transmit buffer. Previous data may still be in the process of being 
transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data 
is moved to the transmit shift register.

1

RO

2

RXOV

Receiver Overrun interrupt flag. This flag is set when the beginning of a 
received character is detected while the receiver buffer is still in use. If this 
occurs, the receiver buffer contents are preserved, and the incoming data is 
lost. Data received by the SPI should be considered undefined if RxOv is set.

0

W1

3

TXUR

Transmitter Underrun interrupt flag. This flag applies only to slave mode 
(Master = 0). In this case, the transmitter must begin sending new data on the 
next input clock if the transmitter is idle. If that data is not available in the 
transmitter holding register at that point, there is no data to transmit and the 
TxUr flag is set. Data transmitted by the SPI should be considered undefined if 
TxUr is set.

0

W1

4

SSA

Slave Select Assert. This flag is set whenever any slave select transitions from 
deasserted to asserted, in both master and slave modes. This allows 
determining when the SPI transmit/receive functions become busy, and allows 
waking up the device from reduced power modes when a slave mode access 
begins. This flag is cleared by software.

0

W1

5

SSD

Slave Select Deassert. This flag is set whenever any asserted slave selects 
transition to deasserted, in both master and slave modes. This allows 
determining when the SPI transmit/receive functions become idle. This flag is 
cleared by software.

0

W1

6

STALLED

Stalled status flag. This indicates whether the SPI is currently in a stall 
condition. 

0

RO

7

ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current 

transfer when the transmitter finishes any activity already in progress, as if the 
EOT flag had been set prior to the last transmission. This capability is included 
to support cases where it is not known when transmit data is written that it will 
be the end of a transfer. The bit is cleared when the transmitter becomes Idle as 
the transfer comes to an end. Forcing an end of transfer in this manner causes 
any specified FrameDelay and TransferDelay to be inserted.

0

RO/W1

8

IDLE

Idle status flag. This bit is 1 whenever the SPI master function is fully idle. This 
means that the transmit holding register is empty and the transmitter is not in 
the process of sending data.

1

RO

31:9

-

Reserved. Read value is undefined, only zero should be written.

NA

NA

Содержание LPC800

Страница 1: ...A F T D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10601 LPC800 User manual Rev 1 0 7 November 2012 Preliminary user manual Document information Info Content Keywords ARM Cortex M0 LPC800...

Страница 2: ...ovided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Preliminary user manual Rev 1 0 7 November 2012 2 of 313 Contact information For more information please visit...

Страница 3: ...processor running at frequencies of up to 30 MHz ARM Cortex M0 built in Nested Vectored Interrupt Controller NVIC Micro Trace Buffer System tick timer Memory 16 kB on chip flash programming memory 4...

Страница 4: ...o SPI controllers with pin functions assigned through the switch matrix One I2C bus interface with open drain full I2C spec fast Modeplus Clock generation 12 MHz internal RC oscillator trimmed to 1 ac...

Страница 5: ...021FN8 DIP8 plastic dual in line package 8 leads 300 mil SOT097 2 LPC811M001FDH16 TSSOP16 plastic thin shrink small outline package 16 leads body width 4 4 mm SOT403 1 LPC812M101FDH16 TSSOP16 plastic...

Страница 6: ...6 of 313 NXP Semiconductors UM10601 Chapter 1 LPC800 Introductory information 1 4 Block diagram Fig 1 LPC800 block diagram 65 0 N 50 257 0 7 67 8 17 5 6 N 63 3 2 72 3 5 2 1 5 7 21 32 5 21752 6 67 0 8...

Страница 7: ...al Rev 1 0 7 November 2012 7 of 313 NXP Semiconductors UM10601 Chapter 1 LPC800 Introductory information 1 5 General description 1 5 1 ARM Cortex M0 core configuration The ARM Cortex M0 core runs at a...

Страница 8: ...2 General description The LPC800 incorporates several distinct memory regions Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset The APB periphe...

Страница 9: ...Micro Trace Buffer The private peripheral bus includes the ARM Cortex M0 peripherals such as the NVIC SysTick and the core control registers Fig 2 LPC800 Memory mapping 3 SHULSKHUDOV 7 057 VHOI ZDNH...

Страница 10: ...tions SVCall and PendSV Support for NMI ARM Cortex M0 Vector table offset register VTOR implemented 3 3 General description The Nested Vectored Interrupt Controller NVIC is an integral part of the Cor...

Страница 11: ...T_IRQ State configurable timer interrupt EVFLAG SCT event 10 MRT_IRQ Multi rate timer interrupt Global MRT interrupt GFLAG0 GFLAG1 GFLAG2 GFLAG3 11 CMP_IRQ Analog comparator interrupt COMPEDGE rising...

Страница 12: ...r manual Rev 1 0 7 November 2012 12 of 313 NXP Semiconductors UM10601 Chapter 3 LPC800 Nested Vectored Interrupt Controller NVIC 29 PININT5_IRQ Pin interrupt 5 or pattern match engine slice 5 interrup...

Страница 13: ...ions through the switch matrix See Section 4 4 No clock configuration is needed The clock to the SYSCON block is always enabled By default the SYSCON block is clocked by the IRC 4 3 1 Set up the PLL T...

Страница 14: ...Main clock source update enable register 3 Select the divider value for the system clock A divider value of 0 disables the system clock Section 4 6 12 System clock divider register 4 Select the memori...

Страница 15: ...clock input the oscillator pins and the external reset input 4 5 General description 4 5 1 Clock generation The system control block facilitates the clock generation Except for the USART clock and th...

Страница 16: ...og comparator For details see the following registers Section 4 6 30 Deep sleep mode configuration register Section 4 6 3 System PLL control register Section 4 6 6 Watchdog oscillator control register...

Страница 17: ...6 27 Pin interrupt select registers 4 6 Register description All system control block registers reside on word address boundaries Details of the registers appear in the description of each function Re...

Страница 18: ...heral clock 3 to the IOCON block for programmable glitch filter 0x0000 0000 Table 27 IOCONCLKDIV2 R W 0x144 Peripheral clock 2 to the IOCON block for programmable glitch filter 0x0000 0000 Table 27 IO...

Страница 19: ...peripheral to operate PDSLEEPCFG R W 0x230 Power down states in deep sleep mode 0xFFFF Table 35 PDAWAKECFG R W 0x234 Power down states for wake up from deep sleep 0xEDF0 Table 36 PDRUNCFG R W 0x238 P...

Страница 20: ...0 reset control 1 0 Assert the USART0 reset 1 Clear the USART0 reset 4 UART1_RST_N USART1 reset control 1 0 Assert the USART reset 1 Clear the USART1 reset 5 UART2_RST_N USART2 reset control 1 0 Asser...

Страница 21: ...L Feedback divider value The division value M is the programmed MSEL value 1 00000 Division ratio M 1 to 11111 Division ratio M 32 0 6 5 PSEL Post divider ratio P The division ratio is 2 P 0 0x0 P 1 0...

Страница 22: ...t_osc_clk using the DIVSEL bits The output clock frequency of the watchdog oscillator can be calculated as wdt_osc_clk Fclkana 2 1 DIVSEL 9 3 kHz to 2 3 MHz nominal values Remark Any setting of the FR...

Страница 23: ...e clock source for the system PLL The SYSPLLCLKUEN register see Section 4 6 9 must be toggled from LOW to HIGH for the update to take effect Table 12 System reset status register SYSRSTSTAT address 0x...

Страница 24: ...the peripherals and the memories Bit 0 of the MAINCLKUEN register see Section 4 6 11 must be toggled from 0 to 1 for the update to take effect 4 6 11 Main clock source update enable register This reg...

Страница 25: ...and peripheral blocks The system clock bit 0 provides the clock for the AHB the APB bridge the ARM Cortex M0 the SYSCON block and the PMU This clock cannot be disabled Table 17 System clock divider re...

Страница 26: ...sable 1 Enable 8 SCT Enables clock for state configurable timer 0 0 Disable 1 Enable 9 WKT Enables clock for self wake up timer 0 0 Disable 1 Enable 10 MRT Enables clock for multi rate timer 0 Disable...

Страница 27: ...oggled from 0 to 1 for the update to take effect 4 6 16 CLKOUT clock source update enable register This register updates the clock source of the CLKOUT pin with the new clock after the CLKOUTSEL regis...

Страница 28: ...e two USART fractional divider registers in the SYSCON block 1 The DIV value programmed in this register is the denominator of the divider used by the fractional rate generator to create the fractiona...

Страница 29: ...23 2 The MULT value programmed in this register is the numerator of the fractional divider value used by the fractional rate generator to create the fractional component to the baud rate See also Sec...

Страница 30: ...re typical values Both the BOD interrupt and the BOD reset depending on the value of bit BODRSTENA in this register can wake up the chip from Sleep Deep sleep and Power down modes See tbd Table 26 POR...

Страница 31: ...arily eliminate it Theoretically the ARM Cortex M0 core should always be able to service an interrupt request within 15 cycles System factors external to the cpu however bus latencies peripheral respo...

Страница 32: ...s the input to the pattern match engine To select a pin for any of the eight pin interrupts or pattern match engine inputs write the GPIO port pin number as 0 to 17 for pins PIO0_0 to PIO0_17 to the I...

Страница 33: ...Pin interrupt select registers PINTSEL 0 7 address 0x4004 8178 PINTSEL0 to 0x4004 8194 PINTSEL7 bit description Bit Symbol Description Reset value 5 0 INTPIN Pin number select for pin interrupt or pat...

Страница 34: ...pts in the NVIC See Table 3 Connection of interrupt sources to the NVIC Table 34 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description Bit Symbol Value Descript...

Страница 35: ...his register The WDTOSC_PD value written to the PDSLEEPCFG register is overwritten if the LOCK bit in the WWDT MOD register see Table 142 is set See Section 12 5 3 for details 4 6 31 Wake up configura...

Страница 36: ...re the power down state takes effect Table 36 Wake up configuration register PDAWAKECFG address 0x4004 8234 bit description Bit Symbol Value Description Reset value 0 IRCOUT_PD IRC oscillator output w...

Страница 37: ...address 0x4004 8238 bit description Bit Symbol Value Description Reset value 0 IRCOUT_PD IRC oscillator output power 0 0 Powered 1 Powered down 1 IRC_PD IRC oscillator power down 0 0 Powered 1 Powered...

Страница 38: ...hen phase and or frequency do not match The loop filter filters these control signals and drives the current controlled oscillator CCO which generates the main clock and optionally two additional phas...

Страница 39: ...detector will be stopped and the dividers will enter a reset state While in Power down mode the lock output will be low to indicate that the PLL is not in lock When the Power down mode is terminated b...

Страница 40: ...ain clock is equivalent to the system clock if the system clock divider SYSAHBCLKDIV is set to one see Table 17 4 7 1 4 2 Power down mode In this mode the internal current reference will be turned off...

Страница 41: ...has no configurable pins In Deep power down only the WAKEUP pin pin PIO0_4 is functional The WAKEUP function can be disabled in the DPDCTRL register to lower the power consumption even more In this c...

Страница 42: ...gisters maintain their internal states The part can wake up on a pulse on the WAKEUP pin or when the self wake up timer times out On wake up the part reboots Remark The LPC800 is in active mode when i...

Страница 43: ...ter Self Wake up Timer WKT time out Enable interrupt in NVIC and STARTERP1 registers Enable low power oscillator in the GPREG4 register in the PCON block Select low power clock for WKT clock in the WK...

Страница 44: ...wer control register PCON address 0x4002 0000 bit description Bit Symbol Value Description Reset value 2 0 PM Power mode 000 0x0 Default The part is in active or sleep mode 0x1 ARM WFI will enter Deep...

Страница 45: ...ow power oscillator in Deep power down mode increases the power consumption Only enable this oscillator if you need the self wake up timer to wake up the part from Deep power down mode You may need th...

Страница 46: ...this bit causes the low power oscillator to remain running during Deep power down mode provided that bit 12 in this register is set as well You must set this bit for the self wake up timer to be able...

Страница 47: ...illator must be powered by using the PDSLEEPCFG register Do not lock the clock source with the IRC selected 5 7 3 Active mode In Active mode the ARM Cortex M0 core and memories are clocked by the syst...

Страница 48: ...zero 3 Use the ARM Cortex M0 Wait For Interrupt WFI instruction 5 7 4 3 Wake up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a r...

Страница 49: ...led in the STARTERP0 register Table 33 and in the NVIC BOD signal if the BOD is enabled in the PDSLEEPCFG register BOD interrupt using the deep sleep interrupt wake up register 1 Table 34 The BOD inte...

Страница 50: ...eep mode see Section 5 7 5 1 The watchdog oscillator can be left running in Power down mode if required for the WWDT The BOD circuit can be left running in Power down mode if required by the applicati...

Страница 51: ...l purpose registers of the PMU block All functional pins are tri stated in Deep power down mode except for the WAKEUP pin Remark Setting bit 3 in the PCON register Table 43 prevents the part from ente...

Страница 52: ...pter 5 LPC800 Reduced power modes and Power Management 2 Once the chip has booted read the deep power down flag in the PCON register Table 43 to verify that the reset was caused by a wake up event fro...

Страница 53: ...rical properties are configurable for each pin Pull up pull down resistor Open drain mode Hysteresis Digital glitch filter with programmable time constant Analog mode for a subset of pins see the LPC8...

Страница 54: ...vable function table to any pin in the IOCON block or enable a special function like an analog input on a specific pin Related links Table 94 Movable functions assign to pins PIO0_0 to PIO_17 through...

Страница 55: ...2C function is selected all three I2C modes Standard mode Fast mode and Fast mode plus are supported A digital glitch filter can be configured for all functions Pins PIO0_10 and PIO0_11 operate as hig...

Страница 56: ...0601 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Preliminary user manual Rev 1 0 7 November 2012 56 of 313 NXP Semiconductors UM10601 Cha...

Страница 57: ...4 0x0000 0090 Table 53 PIO0_3 R W 0x014 I O configuration for pin PIO0_3 SWCLK 0x0000 0090 Table 54 PIO0_2 R W 0x018 I O configuration for pin PIO0_2 SWDIO 0x0000 0090 Table 55 PIO0_11 R W 0x01C I O c...

Страница 58: ...0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mod...

Страница 59: ...Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 60: ...Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 61: ...ull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 62: ...ull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 63: ...ull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 64: ...ull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 65: ...1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 7 Reserved 1 9 8 I2CMODE Selects I2C mode Select Standard mode I2CMODE 00 default or Standard I O functionality I2CMODE 01 if the pin fun...

Страница 66: ...1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 7 Reserved 1 9 8 I2CMODE Selects I2C mode Select Standard mode I2CMODE 00 default or Standard I O functionality I2CMODE 01 if the pin fun...

Страница 67: ...Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0...

Страница 68: ...Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0...

Страница 69: ...ull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 70: ...ull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 71: ...ull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 72: ...ull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 73: ...ull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 74: ...ull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1...

Страница 75: ...Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0...

Страница 76: ...interrupt registers allow pins to be sensed and set individually 7 3 Basic configuration For the GPIO port registers enable the clock to the GPIO port registers in the SYSAHBCLKCTRL register Table 18...

Страница 77: ...ange will be all zeros if the pin is low or all ones if the pin is high regardless of direction masking or alternate function except that pins configured as analog I O always read as zeros Any write w...

Страница 78: ...as analog I O always read as 0s Writing these registers loads the output bits of the pins written to regardless of the Mask register Table 70 GPIO port 0 word pin registers W 0 17 addresses 0xA000 100...

Страница 79: ...Output bits can be cleared by writing ones to these write only registers regardless of MASK registers Table 73 GPIO port 0 pin register PIN0 address 0xA000 2100 bit description Bit Symbol Description...

Страница 80: ...te halfword or word from a Word Pin register The state of multiple pins in a port can be read as a byte halfword or word from a PORT register The state of a selected subset of the pins in a port can b...

Страница 81: ...read from and written to MPORT Ones in MASK force a pin to read as 0 and its output bit to be unaffected by writes to MPORT When a port s MASK register contains all zeros its PORT and MPORT registers...

Страница 82: ...ion can generate its own dedicated interrupt request Any occurrence of a pattern match can be programmed to also generate an RXEV notification to the ARM CPU The RXEV signal can be connected to a pin...

Страница 83: ...ch pin interrupt program the GPIO port pin number into one of the eight PINTSEL registers in the SYSCON block Remark The port pin number serves to identify the pin to the PINTSEL register Any function...

Страница 84: ...en the entire boolean expression is true i e when any minterm is matched The RXEV output is also be routed to GPIO_INT_BMAT pin This allows the GPIO module to provide a rudimentary programmable logic...

Страница 85: ...input IN3 If this combination is detected that is if all three terms are true the interrupt associated with bit slice 2 will be asserted In the second term IN1 IN2 bit slice 3 monitors input IN1 for...

Страница 86: ...Address offset Description Reset value Reference ISEL R W 0x000 Pin Interrupt Mode register 0 Table 80 IENR R W 0x004 Pin interrupt level or rising edge interrupt enable register 0 Table 81 SIENR WO 0...

Страница 87: ...the level interrupt is set 8 6 4 Pin interrupt level or rising edge interrupt clear register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the CIEN...

Страница 88: ...ster For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the SIENF register sets the corresponding bit in the IENF register depending on the pin interrupt...

Страница 89: ...bled for rising edge interrupts All edges are detected for all pins selected by the PINTSELn registers regardless of whether they are interrupt enabled Table 85 Pin interrupt active level or falling e...

Страница 90: ...l Register The pattern match control register contains one bit to select pattern match interrupt generation as opposed to pin interrupts which share the same interrupt request lines and another to ena...

Страница 91: ...Remark Writing any value to either the PMCFG register or the PMSRC register or disabling the pattern match feature by clearing both the SEL_PMATCH and ENA_RXEV bits in the PMCTRL register to zeros wil...

Страница 92: ...rupt input 4 as the source to bit slice 1 0x5 Input 5 Selects pin interrupt input 5 as the source to bit slice 1 0x6 Input 6 Selects pin interrupt input 6 as the source to bit slice 1 0x7 Input 7 Sele...

Страница 93: ...rrupt input 4 as the source to bit slice 5 0x5 Input 5 Selects pin interrupt input 5 as the source to bit slice 5 0x6 Input 6 Selects pin interrupt input 6 as the source to bit slice 5 0x7 Input 7 Sel...

Страница 94: ...sociated with this bit slice will be asserted whenever a match to that product term is detected 2 The next bit slice will start a new independent product term in the boolean expression i e an OR will...

Страница 95: ...s bit slice never contributes to a match should be used to disable any unused bit slices 0x7 Event Match occurs on an event i e when either a rising or falling edge is first detected on the specified...

Страница 96: ...s bit slice never contributes to a match should be used to disable any unused bit slices 0x7 Event Match occurs on an event i e when either a rising or falling edge is first detected on the specified...

Страница 97: ...s bit slice never contributes to a match should be used to disable any unused bit slices 0x7 Event Match occurs on an event i e when either a rising or falling edge is first detected on the specified...

Страница 98: ...eared when the PMCFG or the PMSRC registers are written to 0x2 Falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice...

Страница 99: ...ired SRC0 001 select input 1 for bit slice 0 SRC1 001 select input 1 for bit slice 1 SRC2 010 select input 2 for bit slice 2 SRC3 010 select input 2 for bit slice 3 SRC4 011 select input 3 for bit sli...

Страница 100: ...alog functions 9 3 Basic configuration Once configured no clocks are needed for the switch matrix to function The system clock is needed only to write to or read from the pin assignment registers Afte...

Страница 101: ...he LPC800 package to connect FUNC to 3 Use the pin description table to find the default GPIO function PIO0_n assigned to package pin x m is the pin number 4 Locate the pin assignment register for the...

Страница 102: ...n the LPC800 most functions can be assigned through the switch matrix to any external pin that is not a power or ground pin These functions are called movable functions A few functions like the crysta...

Страница 103: ...ave In for SPI0 PINASSIGN4 Table 100 SPI0_MISO I O Master In Slave Out for SPI0 PINASSIGN4 Table 100 SPI0_SSEL I O Slave select for SPI0 PINASSIGN4 Table 100 SPI1_SCK I O Serial clock for SPI1 PINASSI...

Страница 104: ...ion is associated with one bit in the PINENABLE0 register which selects or deselects the function If a fixed pin function is deselected any movable function can be assigned to its port and pin If a fi...

Страница 105: ...is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_17 0x11 0xFF 15 8 U0_RXD_I U0_RXD function assignment The value is the pin number to be assigned to...

Страница 106: ...are available PIO0_0 0 to PIO0_17 0x11 0xFF 31 24 U2_RXD_I U2_RXD function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_17 0...

Страница 107: ...O SPI1_MOSI function assignment The value is the pin number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_17 0x11 0xFF 15 8 SPI1_MISO_IO SPI1_MISIO function assignm...

Страница 108: ...number to be assigned to this function The following pins are available PIO0_0 0 to PIO0_17 0x11 0xFF Table 104 Pin assign register 8 PINASSIGN8 address 0x4000 C020 bit description Bit Symbol Descript...

Страница 109: ...in Any other movable function can be assigned to pin PIO0_2 4 XTALIN_EN Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin By default th...

Страница 110: ...NXP Semiconductors UM10601 Chapter 9 LPC800 Switch matrix 8 VDDCMP Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin By default the fix...

Страница 111: ...rrupts and the SCT states Match register 0 can be used as an automatic limit In bi directional mode events can be enabled based on the count direction Match events can be held until another qualifying...

Страница 112: ...L registers also control what type of output signal is created 4 If you want to capture a timer value on a capture signal a Configure the register map for capture registers See Table 117 b Create one...

Страница 113: ...a SCT operates as two 16 bit counters or a unified 32 bit counter In the two counter case in addition to the counter value the following operational elements are independent for each half State varia...

Страница 114: ...SCT is used as one 32 bit register for operation as one 32 bit counter timer or as two 16 bit counter timers named L and H The setting of the UNIFY bit is reflected in the register map UNIFY 1 Only o...

Страница 115: ...nter 16 bit Table 112 STOP_H R W 0x012 SCT stop condition register high counter 16 bit Table 112 START R W 0x014 SCT start condition register 0x0000 0000 Table 113 START_L R W 0x014 SCT start conditio...

Страница 116: ...27 MATCHREL_H0 to MATCHREL_H4 R W 0x202 to 0x212 SCT match reload value register 0 to 4 high counter 16 bit REGMOD0_H 0 to REGMODE4_H 0 Table 127 CAPCTRL0 to CAPCTRL4 0x200 to 0x210 SCT capture contro...

Страница 117: ...nters named L and H 1 The SCT operates as a unified 32 bit counter 2 1 CLKMODE SCT clock mode 0 0x0 The bus clock clocks the SCT and prescalers 0x1 The SCT clock is the bus clock but the prescalers ar...

Страница 118: ...n uni directional mode or to change the direction of count in bi directional mode Software can write to set or clear this bit at any time This bit applies to both the higher and lower registers when t...

Страница 119: ...oduce the L or unified counter clock The counter clock is clocked at the rate of the SCT clock divided by PRE_L 1 Remark Clear the counter by writing a 1 to the CLRCTR bit whenever changing the PRE va...

Страница 120: ...n a single 32 bit read or write operation Remark Any event halting the counter disables its operation until software clears the HALT bit or bits in the CTRL register Table 109 10 6 5 SCT stop conditio...

Страница 121: ..._H bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers COUNT_L and COUNT_H Both the L and H registers can be read or written individually or in a single 32...

Страница 122: ...e interrupts modify the state variable The value of a state variable is completely under the control of the application If an application does not use states the value of the state variable remains ze...

Страница 123: ...L and H registers can be read or written individually or in a single 32 bit read or write operation The _L bits registers control the L match capture registers and the _H bits registers control the H...

Страница 124: ...ls one pair of match capture registers register 0 bit 0 register 1 bit 1 register 4 bit 4 0 registers operate as match registers 1 registers operate as capture registers 0 15 5 Reserved 19 16 REGMOD_H...

Страница 125: ...LR3 Set clear operation on output 3 Value 0x3 is reserved Do not program this value 0 0x0 Set and clear do not depend on any counter 0x1 Set and clear are reversed when counter L or the unified counte...

Страница 126: ...ster to request an IRQ 10 6 17 SCT conflict flag register This register records interrupt enabled no change conflict events and provides details of a bus error Writing ones to the NCFLAG bits clears t...

Страница 127: ...value to the Match register used in the first cycle of the counter and a different value to the corresponding Match Reload register used in the second cycle 10 6 19 SCT capture registers 0 to 4 REGMO...

Страница 128: ...escription Reset value 15 0 VALCAP_L When UNIFY 0 read the 16 bit counter value at which this register was last captured When UNIFY 1 read the lower 16 bits of the 32 bit value at which this register...

Страница 129: ...vent is associated with a particular counter by the HEVENT bit in its event control register An event cannot occur when its related counter is halted nor when the current state is not enabled to cause...

Страница 130: ...at least one SCT clock period 0 0x0 LOW 0x1 Rise 0x2 Fall 0x3 HIGH 13 12 COMBMODE Selects how the specified match and I O condition are used and combined 0x0 OR The event occurs when either the specif...

Страница 131: ...tion This field only applies when the counters are operating in BIDIR mode If BIDIR 0 the SCT ignores this field Value 0x3 is reserved 0x0 Direction independent This event is triggered regardless of t...

Страница 132: ...313 NXP Semiconductors UM10601 Chapter 10 LPC800 State Configurable Timer SCT 10 7 Functional description 10 7 1 Match logic 10 7 2 Capture logic 10 7 3 Event selection State variables allow control...

Страница 133: ...10 LPC800 State Configurable Timer SCT 10 7 4 Output generation Figure 13 shows one output slice of the SCT 10 7 5 Interrupt generation The SCT generates one interrupt to the NVIC Fig 12 Event selecti...

Страница 134: ...clears the DOWN bit in the Control register and decrements the counter on the same clock if the counter is enabled in that clock 10 7 7 Match vs I O events Counter operation is complicated by the pres...

Страница 135: ...e the new state defines a new set of events resulting in different actions of the SCT Through multiple cycles of the counter events can change the state multiple times and thus create a large variety...

Страница 136: ...e what the effect of each event is on the SCT outputs in the OUTn_SET or OUTn_CLR registers up to 4 outputs one register per output For each SCT output select which events set or clear this output Mor...

Страница 137: ...n be programmed to capture the counter contents when one or more events occur If the counter is in bidirectional mode the effect of set and clear of an output can be made to depend on whether the coun...

Страница 138: ...vent occurring set the HALT bit and write to the STATE register to change the state value Writing to the STATE register is only allowed when the counter is halted the HALT_L and or HALT_H bits are set...

Страница 139: ...sing the following registers In the SYSAHBCLKCTRL register set bit 10 Table 18 to enable the clock to the register interface Clear the MRT reset using the PRESETCTRL register Table 7 The global MRT in...

Страница 140: ...Ln register IVALUE 1 is reloaded automatically and the timer starts to count down again While the timer is running in repeat interrupt mode you can perform the following actions Change the interval va...

Страница 141: ...VALn register is updated Write a 0 to the INTVALn register and set the LOAD bit to 1 The timer immediately stops counting and moves to the idle state No interrupt is generated when the INTVALn registe...

Страница 142: ...irst idle channel 0 Table 139 IRQ_FLAG R W 0xF8 Global interrupt flag register 0 Table 140 Table 134 Register overview MRT base address 0x4000 4000 Name Access Address offset Description Reset value R...

Страница 143: ...ter TIMER 0 3 address 0x4000 4004 TIMER0 to 0x4000 4034 TIMER3 bit description Bit Symbol Description Reset value 23 0 VALUE Holds the current timer value of the down counter The initial value of the...

Страница 144: ...this register The idle channel register allows you set up the next idle timer without checking the idle state of each timer Table 138 Status register STAT 0 3 address 0x4000 400C STAT0 to 0x4000 403C...

Страница 145: ...for timer channel 0 and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 1 GFLAG1 Monitors the interrupt flag of TIMER1 0 0 No pending interrupt Writing a zero is e...

Страница 146: ...s TWDCLK 224 4 in increments of 4 watchdog clocks Safe watchdog operation Once enabled requires a hardware reset or a Watchdog reset to be disabled Incorrect feed sequence causes immediate watchdog ev...

Страница 147: ...0xFF causes 0xFF to be loaded in the counter Hence the minimum Watchdog interval is TWDCLK 256 4 and the maximum Watchdog interval is TWDCLK 224 4 in multiples of TWDCLK 4 The Watchdog should be used...

Страница 148: ...n the two clock domains works as follows When the MOD and TC registers are updated by APB operations the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain When the wa...

Страница 149: ...5 3 1 Disabling the WWDT clock source If bit 5 in the WWDT MOD register is set the WWDT clock source is locked and can not be disbled either by software or by hardware when Sleep Deep sleep or Power d...

Страница 150: ...nstant register This 24 bit register determines the time out value 0xFF Table 144 FEED WO 0x008 Watchdog feed sequence register Writing 0xAA followed by 0x55 to this register reloads the Watchdog time...

Страница 151: ...is running and has an operating clock source The watchdog oscillator can be configured to keep running in Sleep Deep sleep modes and Power down modes If a watchdog interrupt occurs in Sleep Deep sleep...

Страница 152: ...tchdog register other than writing 0x55 to WDFEED causes an immediate reset interrupt when the Watchdog is enabled and sets the WDTOF flag The reset will be generated during the second PCLK following...

Страница 153: ...emaining upper bits of the counter are all 0 This gives a maximum time of 1 023 watchdog timer counts 4 096 watchdog clocks for the interrupt to occur prior to a watchdog event If WARNINT is 0 the int...

Страница 154: ...owing figures illustrate several aspects of Watchdog Timer operation Table 148 Watchdog Timer Window register WINDOW 0x4000 4018 bit description Bit Symbol Description Reset Value 23 0 WINDOW Watchdog...

Страница 155: ...ed down when not required Interrupt capability 13 3 Basic configuration Configure the analog comparator using the following registers In the SYSAHBCLKCTRL register set bit 19 Table 18 to enable the cl...

Страница 156: ...n to assign the analog comparator output to any pin on the LPC800 package See Section 9 3 2 to enable the analog comparator inputs and the reference voltage input 13 5 General description The analog c...

Страница 157: ...es After the voltage ladder is powered on it requires stabilization time until comparisons using it are accurate Much shorter settling times apply after the LADSEL value is changed and when either or...

Страница 158: ...atrix allowing to capture the time of a voltage crossing or to count crossings in either or both directions See Section 13 3 1 Connect the comparator output to the SCT 13 6 Register description 13 6 1...

Страница 159: ...MP_I2 0x3 Reserved 0x4 Reserved 0x5 Reserved 0x6 Internal reference voltage 0x7 Reserved 19 14 Reserved Write as 0 0 20 EDGECLR Interrupt clear bit To clear the COMPEDGE bit and thus negate the interr...

Страница 160: ...0 Analog comparator 13 6 2 Voltage ladder register This register enables and controls the voltage ladder The fraction of the reference voltage produced by the ladder is programmable in steps of 1 31 T...

Страница 161: ...interface Clear the WKT reset using the PRESETCTRL register Table 7 The WKT interrupt is connected to interrupt 15 in the NVIC Enable the low power oscillator in the PMU Table 45 Enable the IRC and I...

Страница 162: ...termine what the actual frequency is before selecting a time out value to write into the self wake up timer The frequency may still drift however while counting is in progress particularly due to redu...

Страница 163: ...ue it is recommended to read it twice in succession 1 ALARMFLAG Wake up or alarm timer flag 0 No time out The self wake up timer has not timed out Writing a 0 to has no effect 1 Time out The self wake...

Страница 164: ...n or none One transmit and one receive data buffer RTS CTS for hardware signaling for automatic flow control Software flow control can be performed using Delta CTS detect Transmit Disable control and...

Страница 165: ...igure 21 1 Configure the UART clock by writing a value UARTCLKDIV 0 in the USART peripheral clock divider register This is the divided main clock common to all USARTs Section 4 6 14 USART clock divide...

Страница 166: ...nchronous slave mode the USART block can create an interrupt on a received signal even when the USART block receives no clocks from the ARM Cortex M0 core that is in Deep sleep or Power down mode As l...

Страница 167: ...TS pin if the CTS function is connected tbd Remark By enabling or disabling the interrupt in the INTENSET register Table 161 you can customize when the wake up occurs in the USART receive transmit pro...

Страница 168: ...ock directly In synchronous master mode data is transmitted and received using the baud rate clock without division Status information from the transmitter and receiver is saved and provided via the S...

Страница 169: ...ry user manual Rev 1 0 7 November 2012 169 of 313 NXP Semiconductors UM10601 Chapter 15 LPC800 USART0 1 2 U_PCLK UARTCLKDIV 1 MULT DIV Fig 22 USART block diagram 86 57 EORFN 86 57 EORFN 7UDQVPLWWHU 6K...

Страница 170: ...The complete status value can be read here Writing 1s clears some bits in the register Some bits can be cleared by writing a 1 to them 0x000E Table 160 INTENSET R W 0x00C Interrupt Enable read and Se...

Страница 171: ...e reset While Enable 0 all USART interrupts are disabled When Enable is set again CFG and most other control bits remain unchanged For instance when re enabled the USART will immediately generate a Tx...

Страница 172: ...ynchronous mode is selected 12 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode 0 0 Falling edge Un_RXD is sampled on the falling edge of SCLK 1 Rising edge Un_...

Страница 173: ...ave the most significant bit of the data typically the 9th bit 1 When the data MSB bit 1 the receiver treats the incoming data normally generating a received data interrupt Software can then check the...

Страница 174: ...shift register 1 RO 3 TXIDLE Transmitter Idle When 0 indicates that the transmitter is currently in the process of sending data When 1 indicate that the transmitter is not currently in the process of...

Страница 175: ...tatus of that character Three samples of received data are taken in order to determine the value of each received data bit except in synchronous mode This acts as a noise filter if one sample disagree...

Страница 176: ...nterrupt when noise is detected See description of the RXNOISEINT bit in Table 160 0 31 16 Reserved Read value is undefined only zero should be written NA Table 161 USART Interrupt Enable read and set...

Страница 177: ...gister 0 31 16 Reserved Read value is undefined only zero should be written NA Table 162 USART Interrupt Enable clear register INTENCLR address 0x4006 4010 USART0 0x4006 8010 USART1 0x4006 C010 USART2...

Страница 178: ...or status flag This bit is valid when there is a character to be read in the RXDATA register and reflects the status of that character This bit will be set when a parity error is detected in a receive...

Страница 179: ...lowing sequence should be used 1 Make sure the USART is not currently sending or receiving data 2 Disable the USART by writing a 0 to the Enable bit 0 may be written to the entire registers 3 Write th...

Страница 180: ...ed input clocks When not needed the value of 0 can be set for the FRG which will then not divide the input clock The FRG output clock is defined as the inputs clock divided by 1 MULT 256 where MUTL is...

Страница 181: ...1 2 Baud Rate Generator BRG The Baud Rate Generator see Section 15 6 9 is used to divide the base clock to produce a rate 16 times the desired baud rate Typically standard baud rates can be generated...

Страница 182: ...uctors UM10601 Chapter 15 LPC800 USART0 1 2 15 7 3 2 Software flow control Software flow control could include XON XOFF flow control or other mechanisms these are supported by the ability to check the...

Страница 183: ...and Monitor functions Supports both Multi master and Multi master with Slave functions Multiple I2C slave addresses supported in hardware One slave address can be selectively qualified with a bit mask...

Страница 184: ...C pins it completely supports the I2C bus specification up to Fast Mode Plus up to 1 MHz I2C When the I2C function is connected to standard pins that are set to open drain mode a functional I2C bus ca...

Страница 185: ...ption Table 171 I2C Status register STAT address 0x4005 0004 bit description Table 178 I2C Interrupt Status register INTSTAT address 0x4005 0018 bit description Table 174 Interrupt Enable Set and read...

Страница 186: ...Chapter 16 LPC800 I2C bus interface Table 181 Master Data register MSTDAT address 0x4005 0028 bit description Slave function registers Table 182 Slave Control register SLVCTL address 0x4005 0040 bit d...

Страница 187: ...Table 177 INTSTAT R 0x18 Interrupt Status register for Master Slave and Monitor functions 0 Table 178 MSTCTL R W 0x20 Master control register 0 Table 179 MSTTIME R W 0x24 Master timing configuration...

Страница 188: ...hen disabled time out flags will be automatically cleared 0 0 Disabled Time out function is disabled 1 Enabled Time out function is enabled Both types of time out flags will be generated and will caus...

Страница 189: ...de Each value of this field indicates a specific required service for the Master function All other values are reserved 0 RO 0x0 Idle The Master function is available to be used for a new transaction...

Страница 190: ...lave function is stretching the I2C clock This is needed in order to gracefully invoke Deep Sleep or Power down modes during slave operation This read only flag reflects the slave function status in r...

Страница 191: ...s occurred more recently than a bus Stop 0 RO 0 Inactive The Monitor function considers the I2C bus to be inactive 1 Active The Monitor function considers the I2C bus to be active 19 MONIDLE Monitor I...

Страница 192: ...Acknowledged by slave Read data and either continue send a Stop or send a Repeated Start 2 Data can be transmitted Master Transmitter mode Address plus Write was previously sent and Acknowledged by sl...

Страница 193: ...defined only zero should be written NA 4 MSTARBLOSSEN Master Arbitration Loss interrupt Enable 0 0 The MstArbLoss interrupt is disabled 1 The MstArbLoss interrupt is enabled 5 Reserved Read value is u...

Страница 194: ...s disabled 1 The Event time out interrupt is enabled 25 SCLTIMEOUTEN SCL time out interrupt Enable 0 0 The SCL time out interrupt is disabled 1 The SCL time out interrupt is enabled 31 26 Reserved Rea...

Страница 195: ...register The EVENTTIMEOUT status flag can cause an interrupt if enabled to do so by the EVENTTIMEOUTEN bit in the INTENSET register SCLTIMEOUT checks only the time that the SCL signal remains low whi...

Страница 196: ...lags Table 176 time out register TIMEOUT address 0x4005 0010 bit description Bit Symbol Description Reset value 3 0 TOMIN Time out time value bottom four bits These are hard wired to 0xF This gives a...

Страница 197: ...lave Pending 0 10 9 Reserved Read value is undefined only zero should be written NA 11 SLVNOTSTR Slave Not Stretching status 1 14 12 Reserved Read value is undefined only zero should be written NA 15...

Страница 198: ...e written NA Table 179 Master Control register MSTCTL address 0x4005 0020 bit description Bit Symbol Value Description Reset value Table 180 Master Time register MSTTIME address 0x4005 0024 bit descri...

Страница 199: ...SU STO and tHD STA have the same values and are also controlled by MSTSCLHIGH 0 0x0 2 clocks Minimum SCL high time is 2 clock of the I2C clock pre divider 0x1 3 clocks Minimum SCL high time is 3 clock...

Страница 200: ...5 0040 bit description Bit Symbol Value Description Reset Value 0 SlvContinue Slave Continue 0 0 No effect 1 Continue Informs the Slave function to continue to the next operation This must done after...

Страница 201: ...the compare can be affected by the setting of the SLVQUAL0 register see Section 16 6 14 The I2C slave function has 4 address comparators The additional 3 address comparators do not include the addres...

Страница 202: ...s available until the end of the next piece of information from the I2C bus Table 185 Slave address Qualifier 0 register SLVQUAL0 address 0x4005 0058 bit description Bit Symbol Value Description Reset...

Страница 203: ...ks CLKDIV 1 MSTSCLLOW 2 Nominal SCL rate I2C function clock rate SCL high time SCL low time 16 7 2 Time out A time out feature on an I2C interface can be used to detect a stuck bus and potentially do...

Страница 204: ...ard 7 bit address with a Read bit The slave must remember that it had been addressed by the previous write operation and stay selected for the subsequent read with the correct partial I2C address For...

Страница 205: ...A F T D R A UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Preliminary user manual Rev 1 0 7 November 2012 205 of 313 NXP Semicondu...

Страница 206: ...data This allows very versatile operation including any length frames One Slave Select input output with selectable polarity and flexible usage Remark Texas Instruments SSI and National Microwire mod...

Страница 207: ...in the NVIC Any SPI interrupt wakes up the part from sleep mode Enable the SPI interrupt in the INTENSET register Table 192 17 3 1 2 Wake up from Deep sleep or Power down mode Configure the SPI in sl...

Страница 208: ...erial data from this signal MOSI is driven whenever the Master bit in SPInCfg equals 1 regardless of the state of the Enable bit PINASSIGN4 Table 100 SPI0_MISO I O any Master In Slave Out The MISO sig...

Страница 209: ...A LSBF FLEN master enable transfer_delay frame_delay pre_delay post_delay SOT EOT EOF RXIgnore individual interrupt enables Fig 27 SPI block diagram 0 62 026 66 6 3DG LQWHUIDFH 5 6KLIW 5HJLVWHU 6WDWH...

Страница 210: ...rom this register Writing a 1 to any implemented bit position causes that bit to be set 0 Table 192 INTENCLR W 0x010 SPI Interrupt Enable Clear Writing a 1 to any implemented bit position causes the c...

Страница 211: ...I will operate in slave mode SCK MOSI and the SSEL signals are inputs MISO is an output 1 Master mode The SPI will operate in master mode SCK MOSI and the SSEL signals are outputs MISO is an input 3 L...

Страница 212: ...one SPI clock time between SSEL assertion and the first clock edge This is not considered part of the pre delay 0x0 No additional time is inserted 0x1 1 SPI clock time is inserted 0x2 2 SPI clock time...

Страница 213: ...lost Data received by the SPI should be considered undefined if RxOv is set 0 W1 3 TXUR Transmitter Underrun interrupt flag This flag applies only to slave mode Master 0 In this case the transmitter m...

Страница 214: ...ter holding register is available 0 0 No interrupt will be generated when the transmitter holding register is available 1 An interrupt will be generated when data may be written to TXDAT 2 RXOVEN Dete...

Страница 215: ...g bits in the INTENSET register 0 3 TXUREN Writing 1 clears the corresponding bits in the INTENSET register 0 4 SSAEN Writing 1 clears the corresponding bits in the INTENSET register 0 5 SSDEN Writing...

Страница 216: ...a to be transmitted 0 16 TXSSELN Transmit Slave Select This field controls what is output for SSEL in master mode Remark The active state of the SSEL function is configured by bits in the CFG register...

Страница 217: ...s the TXCTL register When control information needs to be changed during transmission the TXDATCTL register should be used see Section 17 6 7 instead of TXDAT Control information can then be written a...

Страница 218: ...Reset value 15 0 Reserved Read value is undefined only zero should be written NA 16 TX SSEL Transmit Slave Select 0x0 19 17 Reserved 0x0 20 EOT End of Transfer 0 21 EOF End of Frame 0 22 RXIGNORE Rece...

Страница 219: ...subject to legal disclaimers NXP B V 2012 All rights reserved Preliminary user manual Rev 1 0 7 November 2012 219 of 313 NXP Semiconductors UM10601 Chapter 17 LPC800 SPI0 1 4 SSA Slave Select Assert 0...

Страница 220: ...e 200 and shown in Figure 28 CPOL and CPHA are configured by bits in the CFG register Section 17 6 1 Table 200 SPI mode summary CPOL CPHA SPI Mode Description SCKrest state SCK data change edge SCK da...

Страница 221: ...at the end of a data frame before SSEL is deasserted Frame_delay delay between data frames when SSEL is not deasserted Transfer_delay minimum duration of SSEL in the deasserted state between transfer...

Страница 222: ...The Frame_delay value controls the amount of time at the end of each frame This delay is inserted when the EOF bit 1 Frame_delay is illustrated by the examples in Figure 30 Note that frame boundaries...

Страница 223: ...7 LPC800 SPI0 1 17 7 2 3 Transfer_delay The Transfer_delay value controls the minimum amount of time that SSEL is deasserted between transfers because the EOT bit 1 When Transfer_delay 0 SSEL may be d...

Страница 224: ...LK_SPIn DIVVAL In slave mode the clock is taken from the SCK input and the SPI clock divider is not used 17 7 4 Slave select The SPI block provides for one Slave Select input in slave mode or output i...

Страница 225: ...se the stall happens just before the final clock edge of data if the next piece of data is not yet available A stall for Master receive can happen when a receiver overrun would otherwise occur if the...

Страница 226: ...7 November 2012 226 of 313 NXP Semiconductors UM10601 Chapter 17 LPC800 SPI0 1 Fig 32 Examples of data stalls 7UDQVPLWWHU VWDOO 3 UDPHBGHOD 3UHBGHOD 3RVWBGHOD FORFN VWDOO 0RGH 32 6 0RGH 32 6 0 62 026...

Страница 227: ...2 x11 x10 x8 x7 x5 x4 x2 x 1 Bit order reverse and 1 s complement programmable setting for input data and CRC sum Programmable seed number setting Supports CPU PIO back to back transfer Accept any siz...

Страница 228: ...ber 2012 228 of 313 NXP Semiconductors UM10601 Chapter 18 LPC800 Cyclic Redundancy Check CRC engine 18 6 Description 18 7 Register description Fig 33 CRC block diagram 7 7 32 5 32 5 32 5 5 7 5 9 56 V...

Страница 229: ...scription Reset value 1 0 CRC_POLY CRC polynom 1X CRC 32 polynomial 01 CRC 16 polynomial 00 CRC CCITT polynomial 00 2 BIT_RVS_WR Data bit order 1 Bit order reverse for CRC_WR_DATA per byte 0 No bit or...

Страница 230: ...ll rights reserved Preliminary user manual Rev 1 0 7 November 2012 230 of 313 NXP Semiconductors UM10601 Chapter 18 LPC800 Cyclic Redundancy Check CRC engine Table 205 CRC data register WR_DATA addres...

Страница 231: ...8 1 CRC CCITT set up Polynomial x16 x12 x5 1 Seed Value 0xFFFF Bit order reverse for data input NO 1 s complement for data input NO Bit order reverse for CRC sum NO 1 s complement for CRC sum NO CRC_...

Страница 232: ...h wait states and for generating the the flash signature 19 4 Register description 19 4 1 Flash configuration register Depending on the system clock frequency access to the flash memory can be configu...

Страница 233: ...h memory access time FLASHTIM 1 is equal to the number of system clocks used for flash access 10 0x0 1 system clock flash access time for system clock frequencies of up to 20 MHz 0x1 2 system clocks f...

Страница 234: ...control automatic signature generation A signature can be generated for any part of the flash memory contents The address range to be used for generation is defined by writing the start address to the...

Страница 235: ...n ns for one AHB clock The SIG_DONE bit in FMSTAT can be polled by software to determine when signature generation is complete After signature generation a 32 bit signature can be read from the FMSW0...

Страница 236: ...oader can execute the ISP command handler or the user application code A LOW level after reset at the PIO0_1 pin is considered as an external hardware request to start the ISP command handler via USAR...

Страница 237: ...d operate the USART and I2C peripherals The structure of the boot ROM APIs is shown in Fig 34 Boot ROM structure Table 211 API calls API Description Reference Flash IAP Flash In Application programmin...

Страница 238: ...of table entries 0 through 6 This causes the checksum of the first 8 table entries to be 0 The bootloader code checksums the first 8 locations in sector 0 of the flash If the result is 0 then executi...

Страница 239: ...reserved Preliminary user manual Rev 1 0 7 November 2012 239 of 313 NXP Semiconductors UM10601 Chapter 20 LPC800 Boot ROM 20 4 4 Boot process flowchart 1 This step is included for backward compatibil...

Страница 240: ...ser board Flash page write and erase supported 21 3 General description 21 3 1 Flash configuration Most IAP and ISP commands operate on sectors and specify sector numbers In addition a page erase comm...

Страница 241: ...ocation and the matching ECC byte are evaluated If the ECC mechanism detects a single error in the fetched data a correction will be applied before data are provided to the CPU When a write request in...

Страница 242: ...sabled This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased Since compare command is disabled in case of partial updates the secondary loader s...

Страница 243: ...2FC 21 4 API description 21 4 1 UART ISP commands The following commands are accepted by the ISP command handler Detailed status codes are supported for each command The command handler sends the retu...

Страница 244: ...r Table 223 Copy RAM to flash C Flash address RAM address number of bytes Table 224 Go G address Mode Table 225 Erase sector s E start sector number end sector number Table 226 Blank check sector s I...

Страница 245: ...ollowed by the CMD_SUCCESS return code Table 220 UART ISP Echo command Command A Input Setting ON 1 OFF 0 Return Code CMD_SUCCESS PARAM_ERROR Description The default setting for echo command is ON Whe...

Страница 246: ...ire sector Remark Once a page has been written to 16 times it is still possible to write to other pages within the same sector without performing a sector erase assuming that those pages have been era...

Страница 247: ...ARED_FOR WRITE_OPERATION BUSY CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to program the flash memory The Prepare Sector s for Write Operation command should p...

Страница 248: ...memory The boot block can not be erased using this command This command only allows erasure of all user sectors when the code read protection is enabled Example E 2 3 CR LF erases the flash sectors 2...

Страница 249: ...rpreted as byte1 Major byte0 Minor Description This command is used to read the boot code version number Table 231 UART ISP Compare command Command M Input Address1 DST Starting flash or RAM address o...

Страница 250: ...urn Code Mnemonic Description 0 CMD_SUCCESS Command is executed successfully Sent by ISP handler only when command given by the host has been completely and successfully executed 1 INVALID_COMMAND Inv...

Страница 251: ...g 0x Define pointer to function type which takes two parameters and returns void Note the IAP returns the result with the base address of the table residing in R1 typedef void IAP unsigned int unsigne...

Страница 252: ...ode Described in Prepare sector s for write operation 50 decimal Table 235 Copy RAM to flash 51 decimal Table 236 Erase sector s 52 decimal Table 237 Blank check sector s 53 decimal Table 238 Read Par...

Страница 253: ...d sector numbers Table 235 IAP Prepare sector s for write operation command Command Prepare sector s for write operation Table 236 IAP Copy RAM to flash command Command Copy RAM to flash Input Command...

Страница 254: ...None Description This command is used to erase a sector or multiple sectors of on chip flash memory The boot sector can not be erased by this command To erase a single sector use the same Start and E...

Страница 255: ...ode 55 decimal Parameters None Return Code CMD_SUCCESS Result Result0 2 bytes of boot code version number Read as byte1 Major byte0 Minor Description This command is used to read the boot code version...

Страница 256: ...pin is not accessible to force the ISP mode Table 243 IAP ReadUID command Command Compare Input Command code 58 decimal Return Code CMD_SUCCESS Result Result0 The first 32 bit word at the lowest addr...

Страница 257: ...Write commands 21 5 1 2 UART ISP response format Return_Code CR LF Response_0 CR LF Response_1 CR LF Response_n CR LF Data Data only for Read commands 21 5 1 3 UART ISP data format The data stream is...

Страница 258: ...P commands is located at 0x1000 0270 The maximum stack usage is 540 byte and grows downwards 21 5 2 4 RAM used by IAP command handler The maximum stack usage in the user allocated stack space is 148 b...

Страница 259: ...e configures the LPC800 for one of the following power modes Default mode corresponding to power configuration after reset CPU performance mode corresponding to optimized processing capability Efficie...

Страница 260: ...river 22 4 API description The power profile API provides functions to configure the system clock and optimize the system setting for lowest power consumption Fig 37 Power profiles pointer structure 3...

Страница 261: ...system AHB clock divider must be set to 1 Table 15 set_pll attempts to find a PLL setup that matches the calling parameters Once a combination of a feedback divider value SYSPLLCTRL M a post divider r...

Страница 262: ...o 25 MHz inclusive The expected system clock Param1 must be between 1 and 50000 kHz inclusive If either of these requirements is not met set_pll returns PLL_INVALID_FREQ and returns Param0 as Result1...

Страница 263: ...e can experience more or less jitter depending on the operating conditions such as power supply and or ambient temperature This is why it is suggested that when a good known clock source is used and a...

Страница 264: ...ULT 0 define PWR_CPU_PERFORMANCE 1 define PWR_EFFICIENCY 2 define PWR_LOW_CURRENT 3 set_power result0 options define PWR_CMD_SUCCESS 0 define PWR_INVALID_FREQ 1 define PWR_INVALID_MODE 2 Fig 39 Power...

Страница 265: ...ne power setting similar to its reset state PWR_CPU_PERFORMANCE configures the microcontroller so that it can provide more processing capability to the application CPU performance is 30 better than th...

Страница 266: ...cannot be found PLL command 0 12000 command 1 25000 command 2 CPU_FREQ_EQU command 3 0 rom pWRD set_pll command result The above code specifies a 12 MHz PLL input clock and a system clock of exactly 2...

Страница 267: ...d 16000 in result 1 The new system clock is 16 MHz 22 5 2 Power control See Section 22 5 1 1 and Section 22 5 2 2 for examples of the power control API 22 5 2 1 Invalid frequency device maximum clock...

Страница 268: ...es 23 3 General description The drivers are callable for use by any application program to send or receive data on the I2C bus With the I2C drivers it is easy to produce working projects using the I2C...

Страница 269: ...FWLRQ WDEOH 520 ULYHU 7DEOH 3WU WR HYLFH 7DEOH 3WU WR HYLFH 7DEOH 3WU WR GULYHU URXWLQHV L FBLVUBKDQGOHU L FBPDVWHUBWUDQVPLWBSROO L FBJHWBVWDWXV Table 250 I2C API calls API call Description Reference...

Страница 270: ...smit_poll I2C_HANDLE_T h_i2c I2C_PARAM ptp I2C_RESULT ptr ErrorCode_t i2c_slave_receive_intr I2C_HANDLE_T h_i2c I2C_PARAM ptp I2C_RESULT ptr ErrorCode_t i2c_slave_transmit_intr I2C_HANDLE_T h_i2c I2C_...

Страница 271: ...Master Transmit Polling Routine I2C Master Transmit Polling Prototype ErrorCode_t i2c_master_transmit_poll I2C_HANDLE_T I2C_PARAM I2C_RESULT Input parameter I2C_HANDLE_T Handle to the allocated SRAM...

Страница 272: ...p_flag 0 When the task is completed the function returns to the line after the call Table 255 I2C Master Transmit Interrupt Routine I2C Master Transmit Interrupt Prototype ErrorCode_t i2c_master_trans...

Страница 273: ...e R W bit 0 is expected in the first byte of the send buffer After the task is finished the slave address with the R W bit 1 is in the first byte of the receive buffer STOP condition is sent at end un...

Страница 274: ...l be completed on an interrupt driven basis When task is completed the callback function is called Table 261 I2C Slave Transmit Interrupt Routine I2C Slave Transmit Interrupt Prototype ErrorCode_t i2c...

Страница 275: ...m unint32 pointer Pointer to allocated SRAM Return I2C_Handle Description Returns a handle to the allocated SRAM area Table 265 I2C Set Bit Rate Routine I2C Set Bit Rate Prototype ErrorCode_t i2c_set_...

Страница 276: ...value Routine I2C time out value Prototype ErrorCode_t i2c_set_timeout I2C_HANDLE_T h_i2c uint32_t timeout Input parameter I2C_HANDLE_T Handle to the allocated SRAM area uint32_t timeout time value i...

Страница 277: ...ucture and a RESULT structure The PARAM structure contains the parameters passed to the I2C ROM driver and the RESULT structure contains the results after the I2C ROM driver is called The PARAM struct...

Страница 278: ...river define ROM_DRIVERS_PTR ROM unsigned int 0x1FFF1FF8 23 5 Functional description 23 5 1 I2C Set up Before calling any setup functions in the I2C ROM the application program is responsible for doin...

Страница 279: ...ROM Driver by making a call to the i2c_get_mem_size function 2 Create the I2C handle by making a call to the i2c_setup function 3 Set the I2C operating frequency by making a call to the i2c_set_bitra...

Страница 280: ...de i2c_master_transmit_intr I2C_HANDLE_T I2C_PARAM I2C_RESULT err_code i2c_master_receive_intr I2C_HANDLE_T I2C_PARAM I2C_RESULT err_code i2c_master_tx_rx_intr I2C_HANDLE_T I2C_PARAM I2C_RESULT Where...

Страница 281: ...e slave address most significant 2 bits with the R W bit 1 The second byte must contain the remaining 8 bit of the slave address The number of bytes to be transmitted should include the first byte of...

Страница 282: ...er of bytes received is updated only for i2c_slave_receive_poll and i2c_slave_receive_intr To initiate a slave mode communication the receive function is called This can be either the polling or inter...

Страница 283: ...D R A UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Preliminary user manual Rev 1 0 7 November 2012 283 of 313 NXP Semiconductors U...

Страница 284: ...ceive multiple characters line in asynchronous UART mode 24 3 General description The UART API handles sending and receiving characters using any of the USART blocks in asynchronous mode Remark Becaus...

Страница 285: ...art_get_line UART_HANDLE_T handle UART_PARAM_T param uint32_t uart_put_line UART_HANDLE_T handle UART_PARAM_T param interrupt functions void uart_isr UART_HANDLE_T handle UARTD_API_T end of structure...

Страница 286: ...ce Description Setup Min UART instance with provided memory and return the handle to this instance Table 274 uart_init Routine uart_init Prototype uint32_t uart_init UART_HANDLE_T handle UART_CONFIG s...

Страница 287: ...ive multiple bytes from UART Table 278 uart_put_line Routine uart_put_line Prototype uint32_t uart_put_line UART_HANDLE_T handle UART_PARAM_T param Input parameter handle The handle to the uart instan...

Страница 288: ...a master on Sync mode uint16_t error_en Bit0 OverrunEn bit1 UnderrunEn bit2 FrameErrEn bit3 ParityErrEn bit4 RxNoiseEn 24 4 10 2 UART_HANDLE_T The handle to the instance of the UART driver Each UART h...

Страница 289: ...reserved Preliminary user manual Rev 1 0 7 November 2012 289 of 313 NXP Semiconductors UM10601 Chapter 24 LPC800 USART API ROM driver routines For uart_put_line function transfer is stopped after reac...

Страница 290: ...wo watchpoints Support for boundary scan and Micro Trace Buffer is available 25 4 Pin description The SWD functions are assigned to pins through the switch matrix The SWD functions are fixed pin funct...

Страница 291: ...wer down mode out of reset etc This pin can be used for other functions such as GPIO but it should not be held LOW on power up or reset Table 282 JTAG boundary scan pin description Function Pin name T...

Страница 292: ...sting follow these steps 1 Erase any user code residing in flash 2 Power up the part with the RESET pin pulled HIGH externally 3 Wait for at least 250 s 4 Pull the RESET pin LOW externally 5 Perform b...

Страница 293: ...on Rev 1 0 7 November 2012 Preliminary user manual Fig 44 Pin configuration DIP8 package LPC810M021FN8 5 6 7 3 2 B 3 2 B 03B 7 2 3 2 B 83 7567 966 6 3 2 B 7 9 6 2 3 2 B 706 3 2 B 03B 1 7 DDD 3 Fig 45...

Страница 294: ...in boundary scan mode only Movable function for the I2C USART SPI and SCT pin functions can be assigned through the switch matrix to any pin that is not power or ground in place of the pin s fixed fu...

Страница 295: ...ock I O PIO0_3 General purpose digital input output pin PIO0_4 WAKEUP TRST 5 4 2 6 I O I PU PIO0_4 General purpose digital input output pin In ISP mode this is the USART0 transmit pin U0_TXD In bounda...

Страница 296: ...and configurable hysteresis 8 5 V tolerant pin providing standard digital I O functions with configurable modes configurable hysteresis and analog I O for the system oscillator When configured as an...

Страница 297: ...select for SPI0 SPI1_SCK I O Serial clock for SPI1 SPI1_MOSI I O Master Out Slave In for SPI1 SPI1_MISO I O Master In Slave Out for SPI1 SPI1_SSEL I O Slave select for SPI1 CTIN_0 I SCT input 0 CTIN_...

Страница 298: ...8 of 313 27 1 Abbreviations 27 2 References 1 DDI0484B_cortex_m0p_r0p0_trm ARM Cortex M0 Technical Reference Manual UM10601 Chapter 27 Supplementary information Rev 1 0 7 November 2012 Preliminary use...

Страница 299: ...d replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life...

Страница 300: ...address 0x4004 80E8 bit description 28 Table 23 USART fractional generator divider value register UARTFRGDIV address 0x4004 80F0 bit description 29 Table 24 USART fractional generator multiplier valu...

Страница 301: ...egister CLR0 address 0xA000 2280 bit description 80 Table 77 GPIO toggle port 0 register NOT0 address 0xA000 2300 bit description 80 Table 78 SCT pin description 83 Table 79 Register overview Pin inte...

Страница 302: ...27 SCT match reload registers 0 to 4 MATCHREL 0 4 address 0x5000 4200 MATCHREL0 to 0x5000 4210 MATCHREL4 bit description REGMODEn bit 0 128 Table 128 SCT capture control registers 0 to 4 CAPCTRL 0 4 a...

Страница 303: ...able Set and read register INTENSET address 0x4005 0008 bit description 193 Table 175 Interrupt Enable Clear register INTENCLR address 0x4005 000C bit description 194 Table 176 time out register TIMEO...

Страница 304: ...29 Part identification numbers 249 Table 230 UART ISP Read Boot Code version number command 249 Table 231 UART ISP Compare command 249 Table 232 UART ISP ReadUID command 249 Table 233 UART ISP Return...

Страница 305: ...g feed with windowed mode enabled 154 Fig 18 Correct watchdog feed with windowed mode enabled 154 Fig 19 Watchdog warning interrupt 154 Fig 20 Comparator block diagram 157 Fig 21 USART clocking 166 Fi...

Страница 306: ...ster 22 4 6 7 System reset status register 23 4 6 8 System PLL clock source select register 23 4 6 9 System PLL clock source update register 24 4 6 10 Main clock source select register 24 4 6 11 Main...

Страница 307: ...e 55 6 4 7 Programmable glitch filter 55 6 5 Register description 57 6 5 1 PIO0_17 register 57 6 5 2 PIO0_13 register 59 6 5 3 PIO0_12 register 60 6 5 4 PIO0_5 register 61 6 5 5 PIO0_4 register 62 6 5...

Страница 308: ...tures 111 10 3 Basic configuration 111 10 3 1 Use the SCT as a simple timer 111 10 4 Pin description 112 10 5 General description 112 10 6 Register description 114 10 6 1 SCT configuration register 11...

Страница 309: ...ption 156 13 5 General description 156 13 5 1 Reference voltages 157 13 5 2 Settling times 157 13 5 3 Interrupts 157 13 5 4 Comparator outputs 158 13 6 Register description 158 13 6 1 Comparator contr...

Страница 310: ...ster 211 17 6 2 SPI Delay register 212 17 6 3 SPI Status register 213 17 6 4 SPI Interrupt Enable read and Set register 214 17 6 5 SPI Interrupt Enable Clear register 215 17 6 6 SPI Receiver Data regi...

Страница 311: ...252 21 4 2 2 Copy RAM to flash IAP 253 21 4 2 3 Erase Sector s IAP 254 21 4 2 4 Blank check sector s IAP 254 21 4 2 5 Read Part Identification number IAP 254 21 4 2 6 Read Boot code version number IAP...

Страница 312: ...structure 277 23 4 23 Error structure 277 23 4 24 I2C Mode 278 23 4 25 I2C ROM driver pointer 278 23 5 Functional description 278 23 5 1 I2C Set up 278 23 5 2 I2C Master mode set up 278 23 5 3 I2C Sla...

Страница 313: ...10601 Chapter 27 Supplementary information NXP B V 2012 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com...

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