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Figure 1. Secure state and Non-secure state view for TrustZone

In summary:

• NS application code “trust” that secure code, does not corrupt/modify NS code or data inadvertently or on purpose to create
malfunction or hazard

• S application code does not “trust” NS application code and disallows access to a CPU-NS

1.1.2 Secure AHB Controller

The LPC55S6x implements second layer of protection with Secure AHB Controller to provide secure trusted execution at system-
level.

With Secure AHB Controller, you can configure security access rules for each peripheral.

By default, CM33 CPU in Secure state (CPU-S) can access the peripherals in both S-state and NS-state. CM33 CPU in Non-
secure state (CPU-NS) can only access the peripherals in NS-state. As shown in 

Fig 2

.

NXP Semiconductors

Background

LPC55S6x Secure GPIO and Usage, Rev. 0, 15 January 2019

Application Note

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Содержание LPC55S6 Series

Страница 1: ...ecure state CPU S can execute instructions from Secure memory S memory but not allowed to execute instructions directly from Non secure memory NS memory However CPU S can access data in both S memory...

Страница 2: ...roller The LPC55S6x implements second layer of protection with Secure AHB Controller to provide secure trusted execution at system level With Secure AHB Controller you can configure security access ru...

Страница 3: ...powerful Like SPI UART and so on a normal GPIO is also a digital peripheral in the MCU Following is a simple block diagram of the normal GPIO The normal GPIO can read a pin state regardless of pin fun...

Страница 4: ...a Secure peripheral which means that this UART is only allowed to be accessed by the Secure world i e code not by the Non secure world However in this case the UART pin states can still be monitored...

Страница 5: ...to generate certain input pattern from external device for secure signaling For the same reason Secure world needs Secure Pin Interrupt Pattern Match Engine PINT so another module named Secure PINT is...

Страница 6: ...separate interrupt in the NVIC Edge sensitive interrupt pins can interrupt on rising or falling edges or both Level sensitive interrupt pins can be HIGH active or LOW active 2 3 2 Secure Pattern Matc...

Страница 7: ...events Non secure world from accessing the Secure GPIO Configure the IOCON block to Secure through Secure AHB Controller It prevents Non secure world from accessing the IOCON Configure the correspondi...

Страница 8: ...T From application perspective the method of using Secure PINT is same as of normal PINT There is one thing that needs extra attention To disable the Non secure world from accessing the Secure PINT re...

Страница 9: ...cable between PC and P6 link on the board for loading and running a demo 4 1 2 Software environment Tool chain IAR embedded workbench 8 30 1 Software package AN_SecureGPIO_Demo zip 4 2 Steps and resu...

Страница 10: ...Configure secure_gpio_s and secure_gpio_ns projects as shown below Figure 15 Configuration of the projects 2 Compile Download Compile secure_gpio_s project first then compile secure_gpio_ns project N...

Страница 11: ...IO and Secure GPIO read all 0 from this pin Press USER button S3 it jumps to Secure world toggle Secure GPIO Mask and then jump back to Non Secure world Press WAKEUP button S2 it will jump to Secure w...

Страница 12: ...lement appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP the NXP logo NXP SECURE CONNECTIONS FOR A SMARTER WORLD COOLFLUX EMBRACE GR...

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