NXP Semiconductors LPC550x, Руководство по проектированию аппаратного обеспечения

Страница: 10 / 24

• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal usage, have a common ground
plane.
• Loops must be made as small as possible to minimize the noise coupled in through the PCB and to keep the parasitics as
small as possible.
• Lay out the GND pattern under crystal unit.
• Do not lay out other signal lines under crystal unit for multi-layered PCB.
4.4 Common suggestions for the PCB layout of oscillator circuit
The crystal oscillator is an analog circuit and must be designed carefully and according to the analog-board layout rules:
• It is recommended to send the PCB to the crystal manufacturer to determine the negative oscillation margin as well as
the optimum regarding CXTAL and CEXTAL capacitors. The datasheet includes recommendations for the tank capacitors
CXTAL and CEXTAL. These values together with the expected PCB, pin, etc. stray capacity values should be used as an
initial point.
• The crystal or resonator oscillator is sensitive to stray capacitance and noise from other signals. It should be placed away
from high-frequency devices and traces in order to avoid and reduce the capacitive coupling between the XTAL and
EXTAL pins and their PCB traces.
• The main oscillation loop current is flowing between the crystal and the load capacitors. This signal path (Oscillator to
CEXTAL to CXTAL to Oscillator) should be kept as short and symmetric tracing as possible. Hence, both the capacitor's
ground connections should be direct always to the closer VSS pin using the cooper-pour ground plane and several vias to
the ground internal layer in the PCB are mandatory.
• The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
Figure 6 shows the recommended placement and routing for the oscillator layout.
Figure 6. Suggested crystal oscillator layout
5 Boot mode configurations
NXP Semiconductors
Boot mode configurations
Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020
Application Note 10 / 24