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Table 10. JTAG and SWD signal description (continued)

JTAG mode

SWD mode

Description

MCU port

Recommendation

—

SWCLK

Serial Wire Debug clock

PIO0_11

Input, Pull-Down

—

SWDIO

Serial Wire Debug I/O

PIO0_12

Input, Pull-Up

RESET

RESET

Reset MCU

Dedicate Pin

Pull-Up

GND

GND

Ground

Dedicate Pins

—

External pull up/down resistors for the JTAG signals can be added in order to increase debugger
connection robustness.

NOTE

Figure 7. SWD connector connections

NXP Semiconductors

Debug and programing interface

Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020

Application Note

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Содержание LPC550x

Страница 1: ...C552x 150 MHz YES YES YES LPC55S6x LPC556x 150 MHz YES YES YES Table 2 LPC55Sxx LPC55xx peripherals Family Flexcomm 50 MHz HS SPI HS USB FS USB CAN FD SDIO LPC55S0x LPC550x 8 1 1 LPC55S1x LPC551x 8 1...

Страница 2: ...N 64 HTQFP 64 VFBGA 98 HLQFP 100 HLQFP 144 VBGA 196 LPC55S0x LPC550x LPC55S1x LPC551x LPC55S2x LPC552x LPC55S6x LPC556x For details see the latest version of the Datasheet and User Manuel on www nxp c...

Страница 3: ...rnal DC DC converter The power and ground pins are described in subsequent sections NXP Semiconductors Power supply Hardware Design Guidelines for LPC55 S xx Microcontrollers Rev 0 30 October 2020 App...

Страница 4: ...Package HTQFP64 VFBGA98 HLFP100 USB0_3V3 USB0 Analog 3 3 V supply 3 3 V 10 uF 10 uF 10 uF 0 1 uF X7R Ceramic USB1_3V3 USB1 Analog 3 3 V supply 3 3 V 10 uF 10 uF 10 uF 0 1 uF X7R Ceramic VDD Single po...

Страница 5: ...Star ground connections VSSA Analog ground FB Feedback node LX DCDC power stage output 3 2 Bulk and decoupling capacitors The effectiveness of the bulk bypass and the de coupling capacitors depends o...

Страница 6: ...lock input bypass mode for clock frequencies of up to 24 MHz Crystal oscillator with 32 768 kHz operating frequency Option for external clock input bypass mode for clock frequencies of up to 100 kHz P...

Страница 7: ...7 Components of the oscillator circuit Symbol Description XTAL Quartz crystal ceramic resonator CX1 Stabilizing capacitor CX2 Stabilizing capacitor For best results it is very critical to select a mat...

Страница 8: ...llator input and output pins of the chip The length of traces in the oscillation circuit should be as short as possible and must not cross other signal lines Ensure that the load capacitors CX1 and CX...

Страница 9: ...board layout and placement of external components influences the optimal values of external load capacitors Therefore it is recommended to fine tune the values of external load capacitors on actual h...

Страница 10: ...oint The crystal or resonator oscillator is sensitive to stray capacitance and noise from other signals It should be placed away from high frequency devices and traces in order to avoid and reduce the...

Страница 11: ...ns Boot mode ISP0 PIO0_5 pin Description Passive boot HIGH The LPC55S6x LPC55S2x LPC552x will look for valid image in the internal flash if no valid image is found the LPC55S6x LPC55S2x LPC552x will e...

Страница 12: ...to debugger easier The JTAG functions TRST TCK TMS TDI and TDO are selected on pins PIO0_2 to PIO0_6 by hardware when the part is in boundary scan mode The JTAG functions CANNOT be used for debug mode...

Страница 13: ...nput Pull Up RESET RESET Reset MCU Dedicate Pin Pull Up GND GND Ground Dedicate Pins External pull up down resistors for the JTAG signals can be added in order to increase debugger connection robustne...

Страница 14: ...ro Magnetic Compatibility EMC reasons although ISO 11898 2 also allows for unshielded cable A maximum line length of 40 meters is specified for CAN at a data rate of 1 Mb However at lower data rates p...

Страница 15: ...es transferred at faster rates up to 8 Mbps Like most others CAN physical transceivers the CANH and CANL are available for the designer to terminate bus depending on the application Figure 9 and Figur...

Страница 16: ...put resistance Fast Input Channels PIO0_16 PIO0_23 1 2 k PIO0_11 PIO0_10 1 2 k PIO0_12 PIO0_15 1 2 k PIO1_0 PIO0_31 1 2 k Standard Input Channels PIO1_9 PIO1_8 1 4 3 6 k 9 Recommendations 9 1 Pin desc...

Страница 17: ...hardware when the part is in boundary scan mode The JTAG functions cannot be used for debug mode NOTE 9 2 Termination of unused pins Table 12 shows how to terminate pins that are not used in the appli...

Страница 18: ...the use of this type of board In this case the major requirement is to ensure a good structure for ground and for the power supply 9 4 General board layout guidelines 9 4 1 Traces recommendations A ri...

Страница 19: ...and single layer PCBs The objective of grounding techniques is to minimize the ground impedance and thus to reduce the potential of the ground loop from circuit back to the supply Route high speed si...

Страница 20: ...his application note does not go into the electromagnetic theory or explain the whys of different techniques used to combat the effects but it considers the effects and solutions most recommended as a...

Страница 21: ...oop of signal and corresponding ground The five main sources of radiation are digital signals propagating on traces current return loop areas inadequate power supply filtering or decoupling transmissi...

Страница 22: ...or connectors 9 4 4 PCB layer stacking To reach signal integrity and performance requirements four layer PCB is recommended for implementing Ethernet applications and systems The following layer stac...

Страница 23: ...words the voltage and current of an input signal must be within the electrical parameter allowed The outcome of violating these specifications causes unexpected behavior stuck operation or a major da...

Страница 24: ...uld implement appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP the NXP logo NXP SECURE CONNECTIONS FOR A SMARTER WORLD COOLFLUX EMB...

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