UM11158
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© NXP B.V. 2019. All rights reserved.
User manual
Rev. 1.2 — 25 April 2019
7 of 24
NXP Semiconductors
UM11158
LPCXpresso55S69 Development Board
J5
Target processor selection for the on-board Debug Probe.
Jumper open (default) the LPC55S69 Target SWD interface enabled.
Normal operating mode where the Target SWD is connected to either
the on-board Link2 Debug Probe or an external Debug Probe.
Jumper shunted, the LPC55S69 Target SWD interface is disabled. Use
this setting only when the on-board Link2 Debug Probe is used to
debug an off-board target MCU.
Not installed
J6
USB host Vbus selection
Note that only one of USB0 or USB1 can be configured as a USB host
port at any given time (this is a board restriction, not a limitation of the
LPC55S69.)
Install jumper in position 1-2 for USB1 (High Speed) to provide Vbus
(i.e. enable USB host capability) (Default)
Install jumper in position 2-3 for USB0 (Full Speed) to provide Vbus (i.e.
enable USB host capability)
1-2 (USB1)
J7
USB host power control selection
This jumper selects routing of USB port power and overcurrent detect
from either the USB0 or USB1 ports of the LPC55S69. Note that only
one of USB0 or USB1 can be configured as a USB host port at any
given time (this is a board restriction, not a limitation of the LPC55S69.)
Leave open when using USB1 (High Speed) as a USB host (Default)
Install jumper for USB0 (Full Speed) to provide Vbus (i.e. enable USB
host capability)
Installed
(USB1)
J10
ISP boot jumper for LPC55S69. Installing this jumper ties port P0_5 to
ground, forcing the LPC55S69 into ISP mode whenever it is reset.
Open
J11
USB1 ID selection: USB1 ID is normally pulled to ground through a
100Kohm resistor. Installing this jumper connects USB1 ID to VBUS.
Open
Not required.
May be
removed in
future versions
J12
USB0 ID selection: USB1 ID is normally pulled to ground through a
100Kohm resistor. Installing this jumper connects USB0 ID to VBUS.
Open
P1
When open (default), the "Bridge" UART and SPI connections from the
Link2 probe are driven to the LPC55S69 target.
Install P1 when using the SPI interface at connector P20 and/or FC0
UART at P8. Note that this disables the Link2 SPI and UART (bridge)
connections.
Open
P4
Target VDD power selection. For Revision A/A1 boards this jumper
must be placed in the 3.3V position (2-3). An external supply voltage to
the LPC55S69 can also be applied through pin 2 of this header
2-3 (3.3V)
P5
Ex5V power
Micro USB connection for power to the LPC55S69 target and
peripheral circuitry (excluding Link2 Debug Probe).
n/a
P6
Link2 Debug Probe connector
Micro USB type B connection for the on-board Link2 Debug Probe.
Note: do not use this connection when using an external Debug Probe.
n/a
P7
10 pin external debug probe / off board target connector
This standard Cortex-M debug connector is used either to (1) connect
and off-board debug probe or (2) to connect an external debug target.
n/a
Table 1.
Indicators, buttons, connectors and LEDs
Circuit
reference
Description
Default
Reference